620 lines
16 KiB
C
620 lines
16 KiB
C
/** @defgroup rcc_file RCC peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32L0xx Reset and Clock Control</b>
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*
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* @version 1.0.0
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*
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* @date November 2014
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*
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* This library supports the Reset and Clock Control System in the STM32F0xx
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* series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/flash.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/rcc.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 2097000;
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uint32_t rcc_apb1_frequency = 2097000;
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uint32_t rcc_apb2_frequency = 2097000;
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_MSI:
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RCC_CR |= RCC_CR_MSION;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI48:
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RCC_CRRCR |= RCC_CRRCR_HSI48ON;
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break;
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case RCC_HSI16:
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RCC_CR |= RCC_CR_HSI16ON;
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break;
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case RCC_LSE:
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RCC_CSR |= RCC_CSR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_MSI:
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RCC_CR &= ~RCC_CR_MSION;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI48:
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RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
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break;
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case RCC_HSI16:
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RCC_CR &= ~RCC_CR_HSI16ON;
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break;
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case RCC_LSE:
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RCC_CSR &= ~RCC_CSR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Oscillator Ready Interrupt Flag
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*
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* Clear the interrupt flag that was set when a clock oscillator became ready
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* to use.
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*
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* @param[in] osc Oscillator ID
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*/
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CICR |= RCC_CICR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CICR |= RCC_CICR_HSERDYC;
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break;
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case RCC_HSI48:
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RCC_CICR |= RCC_CICR_HSI48RDYC;
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break;
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case RCC_HSI16:
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RCC_CICR |= RCC_CICR_HSI16RDYC;
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break;
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case RCC_MSI:
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RCC_CICR |= RCC_CICR_MSIRDYC;
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break;
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case RCC_LSE:
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RCC_CICR |= RCC_CICR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CICR |= RCC_CICR_LSIRDYC;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable the Oscillator Ready Interrupt
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*
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* @param[in] osc Oscillator ID
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*/
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER |= RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER |= RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI48:
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RCC_CIER |= RCC_CIER_HSI48RDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER |= RCC_CIER_HSI16RDYIE;
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break;
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case RCC_MSI:
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RCC_CIER |= RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER |= RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER |= RCC_CIER_LSIRDYIE;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable the Oscillator Ready Interrupt
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*
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* @param[in] osc Oscillator ID
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*/
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER &= ~RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER &= ~RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI48:
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RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER &= ~RCC_CIER_HSI16RDYIE;
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break;
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case RCC_MSI:
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RCC_CIER &= ~RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER &= ~RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER &= ~RCC_CIER_LSIRDYIE;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Read the Oscillator Ready Interrupt Flag
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*
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* @param[in] osc Oscillator ID
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* @returns int. Boolean value for flag set.
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*/
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
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break;
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case RCC_HSI48:
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return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
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break;
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case RCC_HSI16:
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return ((RCC_CIFR & RCC_CIFR_HSI16RDYF) != 0);
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break;
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case RCC_MSI:
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return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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}
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bool rcc_is_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return RCC_CR & RCC_CR_PLLRDY;
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case RCC_HSE:
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return RCC_CR & RCC_CR_HSERDY;
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case RCC_HSI16:
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return RCC_CR & RCC_CR_HSI16RDY;
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case RCC_HSI48:
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return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
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case RCC_MSI:
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return RCC_CR & RCC_CR_MSIRDY;
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case RCC_LSE:
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return RCC_CSR & RCC_CSR_LSERDY;
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case RCC_LSI:
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return RCC_CSR & RCC_CSR_LSIRDY;
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}
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return false;
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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while (!rcc_is_osc_ready(osc));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set HSI48 clock source to the RC48 (CRS)
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*/
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void rcc_set_hsi48_source_rc48(void)
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{
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RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set HSI48 clock source to the PLL
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*/
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void rcc_set_hsi48_source_pll(void)
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{
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RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the Source for the System Clock.
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*
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* @param[in] osc Oscillator ID. Only HSE, HSI16, MSI and PLL have effect.
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*/
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void rcc_set_sysclk_source(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CFGR |= RCC_CFGR_SW_PLL;
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break;
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case RCC_HSE:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSE;
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break;
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case RCC_HSI16:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSI16;
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break;
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case RCC_MSI:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_MSI;
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break;
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case RCC_HSI48:
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case RCC_LSE:
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case RCC_LSI:
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Multiplication Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] factor PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll_multiplier(uint32_t factor)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Division Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] factor PLL multiplication factor @ref rcc_cfgr_pdf
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*/
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void rcc_set_pll_divider(uint32_t factor)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
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RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
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}
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/**
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* Set the pll source.
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* @param pllsrc RCC_CFGR_PLLSRC_HSI16_CLK or RCC_CFGR_PLLSRC_HSE_CLK
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*/
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PLLSRC_HSE_CLK << 16);
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RCC_CFGR = (reg32 | (pllsrc<<16));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB1 Prescale Factor.
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*
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* @note The APB1 clock frequency must not exceed 32MHz.
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*
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* @param[in] ppre APB prescale factor @ref rcc_cfgr_apb1pre
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*/
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void rcc_set_ppre1(uint32_t ppre)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB2 Prescale Factor.
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*
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* @note The APB2 clock frequency must not exceed 32MHz.
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*
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* @param[in] ppre APB prescale factor @ref rcc_cfgr_apb2pre
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*/
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void rcc_set_ppre2(uint32_t ppre)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the AHB Prescale Factor.
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*
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* @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
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*/
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the range of the MSI oscillator
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*
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* @param msi_range desired range @ref rcc_icscr_msirange
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*/
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void rcc_set_msi_range(uint32_t msi_range)
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{
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uint32_t reg32 = RCC_ICSCR & ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
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RCC_ICSCR = reg32 | (msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the LPTIM1 clock source
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*
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* @param lptim1_sel peripheral clock source @ref rcc_ccpipr_lptim1sel
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*/
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void rcc_set_lptim1_sel(uint32_t lptim1_sel)
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{
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RCC_CCIPR &= ~(RCC_CCIPR_LPTIM1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT);
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RCC_CCIPR |= (lptim1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the LPUART1 clock source
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*
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* @param lpuart1_sel periphral clock source @ref rcc_ccpipr_lpuart1sel
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*/
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void rcc_set_lpuart1_sel(uint32_t lpuart1_sel)
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{
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RCC_CCIPR &= ~(RCC_CCIPR_LPUART1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT);
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RCC_CCIPR |= (lpuart1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the USART1 clock source
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*
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* @param usart1_sel periphral clock source @ref rcc_ccpipr_usart1sel
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*/
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void rcc_set_usart1_sel(uint32_t usart1_sel)
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{
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RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT);
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RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the USART2 clock source
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*
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* @param usart2_sel periphral clock source @ref rcc_ccpipr_usartxsel
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*/
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void rcc_set_usart2_sel(uint32_t usart2_sel)
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{
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RCC_CCIPR &= ~(RCC_CCIPR_USART2SEL_MASK << RCC_CCIPR_USART2SEL_SHIFT);
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RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the peripheral clock source
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* @param periph peripheral of desire, eg XXX_BASE
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* @param sel peripheral clock source
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*/
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void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
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{
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uint8_t shift;
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uint32_t mask;
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switch (periph) {
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case LPTIM1_BASE:
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shift = RCC_CCIPR_LPTIM1SEL_SHIFT;
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mask = RCC_CCIPR_LPTIM1SEL_MASK;
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break;
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case I2C3_BASE:
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shift = RCC_CCIPR_I2C3SEL_SHIFT;
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mask = RCC_CCIPR_I2C3SEL_MASK;
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break;
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case I2C1_BASE:
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shift = RCC_CCIPR_I2C1SEL_SHIFT;
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mask = RCC_CCIPR_I2C1SEL_MASK;
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break;
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case LPUART1_BASE:
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shift = RCC_CCIPR_LPUART1SEL_SHIFT;
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mask = RCC_CCIPR_LPUART1SEL_MASK;
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break;
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case USART2_BASE:
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shift = RCC_CCIPR_USART2SEL_SHIFT;
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mask = RCC_CCIPR_USART2SEL_MASK;
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break;
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case USART1_BASE:
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shift = RCC_CCIPR_USART1SEL_SHIFT;
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mask = RCC_CCIPR_USART1SEL_MASK;
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break;
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default:
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return;
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}
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uint32_t reg32 = RCC_CCIPR & ~(mask << shift);
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RCC_CCIPR = reg32 | (sel << shift);
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}
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/* Helper to calculate the frequency of a clksel based clock. */
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static uint32_t rcc_uart_i2c_clksel_freq_hz(uint32_t apb_clk, uint8_t shift) {
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uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_I2C1SEL_MASK;
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uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
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switch (clksel) {
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case RCC_CCIPR_USART1SEL_APB:
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return apb_clk;
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case RCC_CCIPR_USART1SEL_SYS:
|
|
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
|
|
case RCC_CCIPR_USART1SEL_HSI16:
|
|
return 16000000U;
|
|
}
|
|
cm3_assert_not_reached();
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the USART at base specified.
|
|
* @param usart Base address of USART to get clock frequency for.
|
|
*/
|
|
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
|
|
{
|
|
if (usart == LPUART1_BASE) {
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_LPUART1SEL_SHIFT);
|
|
} else if (usart == USART1_BASE) {
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb2_frequency, RCC_CCIPR_USART1SEL_SHIFT);
|
|
} else {
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART2SEL_SHIFT);
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the Timer at base specified.
|
|
* @param timer Base address of TIM to get clock frequency for.
|
|
*/
|
|
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
|
|
{
|
|
/* Handle APB1 timers, and apply multiplier if necessary. */
|
|
if (timer >= TIM2_BASE && timer <= TIM7_BASE) {
|
|
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
|
|
return (ppre1 == RCC_CFGR_PPRE1_NODIV) ? rcc_apb1_frequency
|
|
: 2 * rcc_apb1_frequency;
|
|
} else {
|
|
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
|
|
return (ppre2 == RCC_CFGR_PPRE2_NODIV) ? rcc_apb2_frequency
|
|
: 2 * rcc_apb2_frequency;
|
|
}
|
|
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the I2C device at base specified.
|
|
* @param i2c Base address of I2C to get clock frequency for.
|
|
*/
|
|
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
|
|
{
|
|
if (i2c == I2C1_BASE) {
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C1SEL_SHIFT);
|
|
} else if (i2c == I2C3_BASE) {
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C3SEL_SHIFT);
|
|
} else {
|
|
return rcc_apb1_frequency;
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the SPI device at base specified.
|
|
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
|
|
*/
|
|
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
|
|
if (spi == SPI1_BASE) {
|
|
return rcc_apb2_frequency;
|
|
} else {
|
|
return rcc_apb1_frequency;
|
|
}
|
|
}
|
|
|
|
/** @brief RCC Setup PLL and use it as Sysclk source.
|
|
*
|
|
* @param[in] clock full struct with desired parameters
|
|
*
|
|
*/
|
|
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
|
|
{
|
|
/* Turn on the appropriate source for the PLL */
|
|
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
|
|
rcc_osc_on(RCC_HSE);
|
|
rcc_wait_for_osc_ready(RCC_HSE);
|
|
} else {
|
|
rcc_osc_on(RCC_HSI16);
|
|
rcc_wait_for_osc_ready(RCC_HSI16);
|
|
}
|
|
|
|
rcc_set_hpre(clock->hpre);
|
|
rcc_set_ppre1(clock->ppre1);
|
|
rcc_set_ppre2(clock->ppre2);
|
|
|
|
rcc_periph_clock_enable(RCC_PWR);
|
|
pwr_set_vos_scale(clock->voltage_scale);
|
|
|
|
rcc_osc_off(RCC_PLL);
|
|
while (rcc_is_osc_ready(RCC_PLL));
|
|
|
|
flash_prefetch_enable();
|
|
flash_set_ws(clock->flash_waitstates);
|
|
|
|
/* Set up the PLL */
|
|
rcc_set_pll_multiplier(clock->pll_mul);
|
|
rcc_set_pll_divider(clock->pll_div);
|
|
rcc_set_pll_source(clock->pll_source);
|
|
|
|
rcc_osc_on(RCC_PLL);
|
|
rcc_wait_for_osc_ready(RCC_PLL);
|
|
rcc_set_sysclk_source(RCC_PLL);
|
|
|
|
/* Set the peripheral clock frequencies used. */
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
|
rcc_apb1_frequency = clock->apb1_frequency;
|
|
rcc_apb2_frequency = clock->apb2_frequency;
|
|
}
|
|
|
|
/**@}*/
|