543 lines
11 KiB
C
543 lines
11 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopenstm32/rcc.h>
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#include <libopenstm32/flash.h>
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void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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/* Shouldn't be reached. */
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return -1;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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{
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*reg |= en;
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}
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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{
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*reg &= ~en;
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}
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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{
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*reg |= reset;
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}
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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{
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*reg &= ~clear_reset;
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}
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void rcc_set_sysclk_source(u32 clk)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_multiplication_factor(u32 mul)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18));
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RCC_CFGR = (reg32 | (mul << 18));
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}
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void rcc_set_pll_source(u32 pllsrc)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 16);
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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void rcc_set_pllxtpre(u32 pllxtpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 17);
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RCC_CFGR = (reg32 | (pllxtpre << 17));
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}
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void rcc_set_adcpre(u32 adcpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 14) | (1 << 15));
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RCC_CFGR = (reg32 | (adcpre << 14));
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}
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void rcc_set_ppre2(u32 ppre2)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
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RCC_CFGR = (reg32 | (ppre2 << 11));
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}
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void rcc_set_ppre1(u32 ppre1)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
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RCC_CFGR = (reg32 | (ppre1 << 8));
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}
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void rcc_set_hpre(u32 hpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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RCC_CFGR = (reg32 | (hpre << 4));
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}
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void rcc_set_usbpre(u32 usbpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 22);
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RCC_CFGR = (reg32 | (usbpre << 22));
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}
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u32 rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return ((RCC_CFGR & 0x000c) >> 2);
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}
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/*
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* These functions are setting up the whole clock system for the most common
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* input clock and output clock configurations.
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*/
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void rcc_clock_setup_in_hsi_out_64mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/*
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* Sysclk is running with 64MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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/*
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* Set the PLL multiplication factor to 16.
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* 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz
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*/
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16);
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/* Select HSI/2 as PLL source. */
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hsi_out_48mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* 48 MHz */
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/*
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* Sysclk runs with 48MHz -> 1 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_1WS);
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/*
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* Set the PLL multiplication factor to 12.
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* 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz
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*/
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12);
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/* Select HSI/2 as PLL source. */
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/* Enable external high-speed oscillator 8MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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/*
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* Set the PLL multiplication factor to 9.
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* 8MHz (external) * 9 (multiplier) = 72MHz
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*/
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
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/* Select HSE as PLL source. */
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
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/*
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* External frequency undivided before entering PLL
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* (only valid/needed for HSE).
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*/
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rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/* Enable external high-speed oscillator 16MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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/*
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* Set the PLL multiplication factor to 9.
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* 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz
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*/
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
|
|
|
|
/* Select HSI as PLL source. */
|
|
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
|
|
|
|
/*
|
|
* Divide external frequency by 2 before entering PLL
|
|
* (only valid/needed for HSE).
|
|
*/
|
|
rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2);
|
|
|
|
/* Enable PLL oscillator and wait for it to stabilize. */
|
|
rcc_osc_on(PLL);
|
|
rcc_wait_for_osc_ready(PLL);
|
|
|
|
/* Select PLL as SYSCLK source. */
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
|
|
}
|
|
|
|
void rcc_backupdomain_reset(void)
|
|
{
|
|
/* Set the backup domain software reset. */
|
|
RCC_BDCR |= RCC_BDCR_BDRST;
|
|
|
|
/* Clear the backup domain software reset. */
|
|
RCC_BDCR &= ~RCC_BDCR_BDRST;
|
|
}
|