183 lines
5.8 KiB
C
183 lines
5.8 KiB
C
/** @defgroup VF6xx_uart_defines UART Defines
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*
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* @brief <b>Defined Constants and Types for the VF6xx UART Module</b>
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*
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* @ingroup VF6xx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2014
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* Stefan Agner <stefan@agner.ch>
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*
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* @date 01 July 2014
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_VF6XX_UART_H
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#define LIBOPENCM3_VF6XX_UART_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/vf6xx/memorymap.h>
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/* --- Convenience macros -------------------------------------------------- */
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/****************************************************************************/
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/** @defgroup uart_reg_base UART register base addresses
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@ingroup VF6xx_uart_defines
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@{*/
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#define UART0 UART0_BASE
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#define UART1 UART1_BASE
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#define UART2 UART2_BASE
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#define UART3 UART3_BASE
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#define UART4 UART4_BASE
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#define UART5 UART5_BASE
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/* --- UART registers ------------------------------------------------------ */
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#define UART_BDH(uart_base) MMIO8((uart_base) + 0x00)
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#define UART_BDL(uart_base) MMIO8((uart_base) + 0x01)
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#define UART_C1(uart_base) MMIO8((uart_base) + 0x02)
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#define UART_C2(uart_base) MMIO8((uart_base) + 0x03)
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#define UART_S1(uart_base) MMIO8((uart_base) + 0x04)
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#define UART_S2(uart_base) MMIO8((uart_base) + 0x05)
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#define UART_C3(uart_base) MMIO8((uart_base) + 0x06)
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#define UART_D(uart_base) MMIO8((uart_base) + 0x07)
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#define UART_MA1(uart_base) MMIO8((uart_base) + 0x08)
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#define UART_MA2(uart_base) MMIO8((uart_base) + 0x09)
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#define UART_C4(uart_base) MMIO8((uart_base) + 0x0A)
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#define UART_C5(uart_base) MMIO8((uart_base) + 0x0B)
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#define UART_ED(uart_base) MMIO8((uart_base) + 0x0C)
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#define UART_MODEM(uart_base) MMIO8((uart_base) + 0x0D)
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/* Incomplete */
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/* --- CCM values -....----------------------------------------------------- */
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/* BDH: Baud Rate Register High */
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#define UART_BDH_LBKDIE (1 << 7)
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#define UART_BDH_RXEDGIE (1 << 6)
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#define UART_BDH_SBR_MASK 0x1f
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/* BDL: Baud Rate Register Low */
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#define UART_BDL_SBR_MASK 0xff
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/* C1: Control register 1 */
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#define UART_C1_LOOPS (1 << 7)
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#define UART_C1_RSRC (1 << 5)
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#define UART_C1_M (1 << 4)
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#define UART_C1_WAKE (1 << 3)
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#define UART_C1_ILT (1 << 2)
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#define UART_C1_PE (1 << 1)
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#define UART_C1_PT (1 << 0)
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/* C2: Control register 2 */
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#define UART_C2_TIE (1 << 7)
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#define UART_C2_TCIE (1 << 6)
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#define UART_C2_RIE (1 << 5)
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#define UART_C2_ILIE (1 << 4)
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#define UART_C2_TE (1 << 3)
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#define UART_C2_RE (1 << 2)
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#define UART_C2_RWU (1 << 1)
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#define UART_C2_SBK (1 << 0)
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/* S1: Status register 1 */
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#define UART_S1_TDRE (1 << 7)
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#define UART_S1_TC (1 << 6)
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#define UART_S1_RDRF (1 << 5)
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#define UART_S1_IDLE (1 << 4)
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#define UART_S1_OR (1 << 3)
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#define UART_S1_NF (1 << 2)
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#define UART_S1_FE (1 << 1)
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#define UART_S1_PF (1 << 0)
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/* S2: Status register 2 */
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#define UART_S2_LBKDIF (1 << 7)
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#define UART_S2_RXEDGIF (1 << 6)
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#define UART_S2_MSBF (1 << 5)
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#define UART_S2_RXINV (1 << 4)
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#define UART_S2_RWUID (1 << 3)
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#define UART_S2_BRK13 (1 << 2)
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#define UART_S2_LBKDE (1 << 1)
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#define UART_S2_RAF (1 << 0)
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/* C3: Control register 3 */
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#define UART_C3_R8 (1 << 7)
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#define UART_C3_T8 (1 << 6)
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#define UART_C3_TXDIR (1 << 5)
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#define UART_C3_TXINV (1 << 4)
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#define UART_C3_ORIE (1 << 3)
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#define UART_C3_NEIE (1 << 2)
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#define UART_C3_FEIE (1 << 1)
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#define UART_C3_PEIE (1 << 0)
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/* MODEM: Modem configuration register */
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#define UART_MODEM_RXRTSE (1 << 3)
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#define UART_MODEM_TXRTSPOL (1 << 2)
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#define UART_MODEM_TXRTSE (1 << 1)
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#define UART_MODEM_TXCTSE (1 << 0)
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/****************************************************************************/
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/** @defgroup uart_parity UART Parity Selection
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@ingroup VF6xx_uart_defines
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@{*/
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#define UART_PARITY_NONE 0x00
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#define UART_PARITY_EVEN UART_C1_PE
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#define UART_PARITY_ODD (UART_C1_PE | UART_C1_PT)
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/**@}*/
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#define UART_PARITY_MASK 0x3
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/* CR3_CTSE/CR3_RTSE combined values */
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/****************************************************************************/
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/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
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@ingroup STM32F_usart_defines
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@{*/
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#define UART_FLOWCONTROL_NONE 0x00
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#define UART_FLOWCONTROL_RTS UART_MODEM_RXRTSE
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#define UART_FLOWCONTROL_CTS UART_MODEM_TXCTSE
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#define UART_FLOWCONTROL_RTS_CTS (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE)
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/**@}*/
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#define UART_FLOWCONTROL_MASK (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE)
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/* --- Function prototypes ------------------------------------------------- */
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#include <libopencm3/cm3/common.h>
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BEGIN_DECLS
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void uart_enable(uint32_t uart);
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void uart_disable(uint32_t uart);
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void uart_set_baudrate(uint32_t uart, uint32_t baud);
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void uart_set_parity(uint32_t uart, uint8_t parity);
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void uart_set_flow_control(uint32_t uart, uint8_t flowcontrol);
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void uart_send(uint32_t uart, uint8_t data);
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void uart_send_blocking(uint32_t usart, uint8_t data);
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void uart_wait_send_ready(uint32_t uart);
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uint8_t uart_recv(uint32_t uart);
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uint8_t uart_recv_blocking(uint32_t uart);
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void uart_wait_recv_ready(uint32_t uart);
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END_DECLS
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#endif
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