217 lines
9.1 KiB
C
217 lines
9.1 KiB
C
/** @defgroup dmamux_defines DMAMUX Defines
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@ingroup STM32G4xx_defines
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@brief Defined Constants and Types for the STM32G4xx DMAMUX
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@version 1.0.0
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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/**@{*/
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#include <libopencm3/stm32/common/dmamux_common_all.h>
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/** @defgroup dmamux_reg_base DMAMUX register base addresses
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* @{
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*/
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#define DMAMUX1 DMAMUX_BASE
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/**@}*/
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/* --- DMAMUX_CxCR values ------------------------------------ */
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/** @defgroup dmamux_cxcr_sync_id SYNCID Synchronization input selected
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@{*/
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE0 0
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE1 1
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE2 2
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE3 3
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE4 4
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE5 5
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE6 6
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE7 7
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE8 8
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE9 9
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE10 10
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE11 11
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE12 12
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE13 13
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE14 14
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE15 15
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH0_EVT 16
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH1_EVT 17
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH2_EVT 18
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH3_EVT 19
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#define DMAMUX_CxCR_SYNC_ID_LPTIM1_OUT 20
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/**@}*/
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/** @defgroup dmamux_cxcr_dmareq_id DMAREQID DMA request line selected
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@{*/
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#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN0 1
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#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN1 2
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#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN2 3
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#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN3 4
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#define DMAMUX_CxCR_DMAREQ_ID_ADC1 5
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#define DMAMUX_CxCR_DMAREQ_ID_DAC1_CH1 6
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#define DMAMUX_CxCR_DMAREQ_ID_DAC1_CH2 7
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#define DMAMUX_CxCR_DMAREQ_ID_TIM6_UP 8
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#define DMAMUX_CxCR_DMAREQ_ID_TIM7_UP 9
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#define DMAMUX_CxCR_DMAREQ_ID_SPI1_RX 10
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#define DMAMUX_CxCR_DMAREQ_ID_SPI1_TX 11
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#define DMAMUX_CxCR_DMAREQ_ID_SPI2_RX 12
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#define DMAMUX_CxCR_DMAREQ_ID_SPI2_TX 13
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#define DMAMUX_CxCR_DMAREQ_ID_SPI3_RX 14
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#define DMAMUX_CxCR_DMAREQ_ID_SPI3_TX 15
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#define DMAMUX_CxCR_DMAREQ_ID_I2C1_RX 16
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#define DMAMUX_CxCR_DMAREQ_ID_I2C1_TX 17
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#define DMAMUX_CxCR_DMAREQ_ID_I2C2_RX 18
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#define DMAMUX_CxCR_DMAREQ_ID_I2C2_TX 19
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#define DMAMUX_CxCR_DMAREQ_ID_I2C3_RX 20
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#define DMAMUX_CxCR_DMAREQ_ID_I2C3_TX 21
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#define DMAMUX_CxCR_DMAREQ_ID_I2C4_RX 22
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#define DMAMUX_CxCR_DMAREQ_ID_I2C4_TX 23
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#define DMAMUX_CxCR_DMAREQ_ID_UART1_RX 24
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#define DMAMUX_CxCR_DMAREQ_ID_UART1_TX 25
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#define DMAMUX_CxCR_DMAREQ_ID_UART2_RX 26
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#define DMAMUX_CxCR_DMAREQ_ID_UART2_TX 27
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#define DMAMUX_CxCR_DMAREQ_ID_UART3_RX 28
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#define DMAMUX_CxCR_DMAREQ_ID_UART3_TX 29
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#define DMAMUX_CxCR_DMAREQ_ID_UART4_RX 30
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#define DMAMUX_CxCR_DMAREQ_ID_UART4_TX 31
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#define DMAMUX_CxCR_DMAREQ_ID_UART5_RX 32
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#define DMAMUX_CxCR_DMAREQ_ID_UART5_TX 33
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#define DMAMUX_CxCR_DMAREQ_ID_LPUART1_RX 34
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#define DMAMUX_CxCR_DMAREQ_ID_LPUART1_TX 35
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#define DMAMUX_CxCR_DMAREQ_ID_ADC2 36
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#define DMAMUX_CxCR_DMAREQ_ID_ADC3 37
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#define DMAMUX_CxCR_DMAREQ_ID_ADC4 38
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#define DMAMUX_CxCR_DMAREQ_ID_ADC5 39
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#define DMAMUX_CxCR_DMAREQ_ID_QUADSPI 40
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#define DMAMUX_CxCR_DMAREQ_ID_DAC2_CH1 41
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH1 42
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH2 43
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH3 44
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH4 45
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_UP 46
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_TRIG 47
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#define DMAMUX_CxCR_DMAREQ_ID_TIM1_COM 48
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_CH1 49
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_CH2 50
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_CH3 51
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_CH4 52
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_UP 53
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_TRIG 54
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#define DMAMUX_CxCR_DMAREQ_ID_TIM8_COM 55
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#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH1 56
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#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH2 57
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#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH3 58
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#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH4 59
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#define DMAMUX_CxCR_DMAREQ_ID_TIM2_UP 60
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#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH1 61
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#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH2 62
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#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH3 63
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#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH4 64
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#define DMAMUX_CxCR_DMAREQ_ID_TIM3_UP 65
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#define DMAMUX_CxCR_DMAREQ_ID_TIM3_TRIG 66
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#define DMAMUX_CxCR_DMAREQ_ID_TIM4_CH1 67
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#define DMAMUX_CxCR_DMAREQ_ID_TIM4_CH2 68
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#define DMAMUX_CxCR_DMAREQ_ID_TIM4_CH3 69
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#define DMAMUX_CxCR_DMAREQ_ID_TIM4_CH4 70
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#define DMAMUX_CxCR_DMAREQ_ID_TIM4_UP 71
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#define DMAMUX_CxCR_DMAREQ_ID_TIM5_CH1 72
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#define DMAMUX_CxCR_DMAREQ_ID_TIM5_CH2 73
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#define DMAMUX_CxCR_DMAREQ_ID_TIM5_CH3 74
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#define DMAMUX_CxCR_DMAREQ_ID_TIM5_CH4 75
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#define DMAMUX_CxCR_DMAREQ_ID_TIM5_UP 76
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#define DMAMUX_CxCR_DMAREQ_ID_TIM5_TRIG 77
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#define DMAMUX_CxCR_DMAREQ_ID_TIM15_CH1 78
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#define DMAMUX_CxCR_DMAREQ_ID_TIM15_UP 79
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#define DMAMUX_CxCR_DMAREQ_ID_TIM15_TRIG 80
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#define DMAMUX_CxCR_DMAREQ_ID_TIM15_COM 81
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#define DMAMUX_CxCR_DMAREQ_ID_TIM16_CH1 82
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#define DMAMUX_CxCR_DMAREQ_ID_TIM16_UP 83
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#define DMAMUX_CxCR_DMAREQ_ID_TIM17_CH1 84
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#define DMAMUX_CxCR_DMAREQ_ID_TIM17_UP 85
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_CH1 86
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_CH2 87
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_CH3 88
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_CH4 89
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_UP 90
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#define DMAMUX_CxCR_DMAREQ_ID_AES_IN 91
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#define DMAMUX_CxCR_DMAREQ_ID_AES_OUT 92
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_TRIG 93
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#define DMAMUX_CxCR_DMAREQ_ID_TIM20_COM 94
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_MASTER 95
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_TIMA 96
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_TIMB 97
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_TIMC 98
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_TIMD 99
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_TIME 100
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#define DMAMUX_CxCR_DMAREQ_ID_HRTIM_TIMF 101
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#define DMAMUX_CxCR_DMAREQ_ID_DAC3_CH1 102
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#define DMAMUX_CxCR_DMAREQ_ID_DAC3_CH2 103
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#define DMAMUX_CxCR_DMAREQ_ID_DAC4_CH1 104
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#define DMAMUX_CxCR_DMAREQ_ID_DAC4_CH2 105
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#define DMAMUX_CxCR_DMAREQ_ID_SPI4_RX 106
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#define DMAMUX_CxCR_DMAREQ_ID_SPI4_TX 107
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#define DMAMUX_CxCR_DMAREQ_ID_SAI1_A 108
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#define DMAMUX_CxCR_DMAREQ_ID_SAI1_B 109
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#define DMAMUX_CxCR_DMAREQ_ID_FMAC_READ 110
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#define DMAMUX_CxCR_DMAREQ_ID_FMAC_WRITE 111
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#define DMAMUX_CxCR_DMAREQ_ID_CORDIC_READ 112
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#define DMAMUX_CxCR_DMAREQ_ID_CORDIC_WRITE 113
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#define DMAMUX_CxCR_DMAREQ_ID_UCPD1_RX 114
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#define DMAMUX_CxCR_DMAREQ_ID_UCPD1_TX 115
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/**@}*/
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/* --- DMAMUX_RGxCR values ----------------------------------- */
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/** @defgroup dmamux_rgxcr_sig_id SIGID DMA request trigger input selected
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@{*/
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE0 0
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE1 1
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE2 2
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE3 3
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE4 4
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE5 5
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE6 6
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE7 7
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE8 8
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE9 9
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE10 10
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE11 11
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE12 12
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE13 13
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE14 14
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#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE15 15
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH0_EVT 16
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH1_EVT 17
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH2_EVT 18
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#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH3_EVT 19
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#define DMAMUX_CxCR_SYNC_ID_LPTIM1_OUT 20
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/**@}*/
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/**@}*/
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