110 lines
3.9 KiB
C
110 lines
3.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SAM3X_PWM_H
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#define SAM3X_PWM_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/sam/memorymap.h>
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/* --- Pulse Width Modulation (PWM) registers ----------------------- */
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#define PWM_CLK MMIO32(PWM_BASE + 0x0000)
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#define PWM_ENA MMIO32(PWM_BASE + 0x0004)
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#define PWM_DIS MMIO32(PWM_BASE + 0x0008)
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#define PWM_SR MMIO32(PWM_BASE + 0x000C)
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#define PWM_IER1 MMIO32(PWM_BASE + 0x0010)
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#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014)
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#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018)
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#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C)
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#define PWM_SCM MMIO32(PWM_BASE + 0x0020)
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/* 0x0024 - Reserved */
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#define PWM_SCUC MMIO32(PWM_BASE + 0x0028)
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#define PWM_SCUP MMIO32(PWM_BASE + 0x002C)
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#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030)
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#define PWM_IER2 MMIO32(PWM_BASE + 0x0034)
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#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038)
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#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C)
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#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040)
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#define PWM_OOV MMIO32(PWM_BASE + 0x0044)
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#define PWM_OS MMIO32(PWM_BASE + 0x0048)
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#define PWM_OSS MMIO32(PWM_BASE + 0x004C)
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#define PWM_OSC MMIO32(PWM_BASE + 0x0050)
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#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054)
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#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058)
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#define PWM_FMR MMIO32(PWM_BASE + 0x005C)
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#define PWM_FSR MMIO32(PWM_BASE + 0x0060)
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#define PWM_FCR MMIO32(PWM_BASE + 0x0064)
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#define PWM_FPV MMIO32(PWM_BASE + 0x0068)
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#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C)
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#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070)
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/* 0x0074:0x0078 - Reserved */
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#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C)
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#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080)
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/* 0x0084:0x00AC - Reserved */
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#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0)
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/* 0x00B4:0x00E0 - Reserved */
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#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4)
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#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8)
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/* 0x00EC:0x00FC - Reserved */
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/* 0x0100:0x012C - Reserved */
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#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x))
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#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x))
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#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x))
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#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x))
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/* 0x01B0:0x01FC - Reserved */
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#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x))
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#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x))
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#if defined(SAM3X)
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# define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x))
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# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x))
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# define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x))
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# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x))
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# define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x))
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# define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x))
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#elif defined(SAM3N)
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# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x))
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# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x))
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# define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x))
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#else
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# error "Processor family not defined."
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#endif
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static inline void pwm_set_period(int ch, uint32_t period)
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{
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PWM_CPRD(ch) = period;
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}
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static inline void pwm_set_duty(int ch, uint32_t duty)
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{
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PWM_CDTY(ch) = duty;
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}
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static inline void pwm_enable(int ch)
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{
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PWM_ENA = 1 << ch;
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}
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static inline void pwm_disable(int ch)
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{
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PWM_DIS = 1 << ch;
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}
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#endif
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