108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/** @defgroup rcc_defines RCC Defines
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*
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* @brief <b>Defined Constants and Types for the LM3S Reset and Clock
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* Control</b>
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*
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* @ingroup LM3S_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2009
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* Daniele Lacamera \<root at danielinux dot net\>
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*
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* @date 21 November 2015
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Daniele Lacamera <root@danielinux.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/cm3/common.h>
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_RIS MMIO32(0x400FE050)
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#define RCC_CR MMIO32(0x400FE060)
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#define RCC2_CR MMIO32(0x400FE070)
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/* RCC1 bits */
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#define RCC_SYSDIV_MASK (0x0F << 23)
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#define RCC_SYSDIV_12_5MHZ (0x0F << 23)
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#define RCC_SYSDIV_50MHZ (0x03 << 23)
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#define RCC_USESYSDIV (1 << 22)
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#define RCC_USEPWMDIV (1 << 20)
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#define RCC_PWMDIV_MASK (0x07 << 17)
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#define RCC_PWMDIV_64 (0x07 << 17)
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#define RCC_OFF (1 << 13)
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#define RCC_BYPASS (1 << 11)
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#define RCC_XTAL_MASK (0x0F << 6)
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/* For other values, see datasheet section 23.2.2 - table 23-9 */
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#define RCC_XTAL_6MHZ_RESET (0x0B << 6)
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#define RCC_XTAL_8MHZ_400MHZ (0x0D << 6)
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#define RCC_OSCRC_MASK (0x03 << 4)
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#define RCC_OSCRC_MOSC (0x00 << 4)
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#define RCC_OSCRC_IOSC (0x01 << 4)
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#define RCC_OSCRC_IOSC_Q (0x02 << 4)
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#define RCC_OSCRC_30KHZ (0x03 << 4)
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#define RCC_IOSCDIS (1 << 1)
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#define RCC_MOSCDIS (1 << 0)
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/* RCC2 bits */
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#define RCC2_USERRCC2 (1 << 31)
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#define RCC2_SYSDIV2_MASK 0x7f
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#define RCC2_SYSDIV2_SHIFT 23
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#define RCC2_OFF (1 << 13)
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#define RCC2_BYPASS (1 << 11)
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/* RIS bit */
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#define RIS_PLLLRIS (1 << 6)
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/* From Datasheet description for reset values
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* Section 6.4 - Register Descriptions
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*/
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/* Register 8: RCC
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* Type R/W, reset 0x078E.3AD1
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*/
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#define RCC_RESET_VALUE (0x078E3AD1)
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/* Register 10: RCC2
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* Type R/W, reset 0x0780.2810
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*/
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#define RCC2_RESET_VALUE (0x07802810)
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BEGIN_DECLS
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int rcc_clock_setup_in_xtal_8mhz_out_50mhz(void);
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END_DECLS
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#endif
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