146 lines
4.9 KiB
C
146 lines
4.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SAM3X_PMC_H
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#define SAM3X_PMC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/sam/memorymap.h>
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/* --- Power Management Controller (PMC) registers ----------------------- */
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#define PMC_SCER MMIO32(PMC_BASE + 0x0000)
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#define PMC_SCDR MMIO32(PMC_BASE + 0x0004)
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#define PMC_SCSR MMIO32(PMC_BASE + 0x0008)
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/* 0x000C - Reserved */
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#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010)
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#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014)
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#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018)
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#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
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#define CKGR_MOR MMIO32(PMC_BASE + 0x0020)
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#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024)
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#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028)
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/* 0x002C - Reserved */
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#define PMC_MCKR MMIO32(PMC_BASE + 0x0030)
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/* 0x0034 - Reserved */
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#define PMC_USB MMIO32(PMC_BASE + 0x0038)
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/* 0x003C - Reserved */
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#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040)
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#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044)
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#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048)
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/* 0x004C-0x005C - Reserved */
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#define PMC_IER MMIO32(PMC_BASE + 0x0060)
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#define PMC_IDR MMIO32(PMC_BASE + 0x0064)
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#define PMC_SR MMIO32(PMC_BASE + 0x0068)
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#define PMC_IMR MMIO32(PMC_BASE + 0x006C)
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#define PMC_FSMR MMIO32(PMC_BASE + 0x0070)
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#define PMC_FSPR MMIO32(PMC_BASE + 0x0074)
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#define PMC_FOCR MMIO32(PMC_BASE + 0x0078)
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/* 0x007C-0x00E0 - Reserved */
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#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4)
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#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8)
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/* 0x00EC-0x00FC - Reserved */
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#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100)
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#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104)
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#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108)
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#define PMC_PCR MMIO32(PMC_BASE + 0x010C)
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/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */
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/* Bit [31:22] - Reserved */
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#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20)
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/* Bit [19:17] - Reserved */
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#define CKGR_CKGR_UPLLEN (0x01 << 16)
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/* Bit [15:0] - Reserved */
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/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */
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/* Bit [31:26] - Reserved */
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#define CKGR_MOR_CFDEN (0x01 << 25)
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#define CKGR_MOR_MOSCSEL (0x01 << 24)
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#define CKGR_MOR_KEY (0x37 << 16)
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#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8)
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/* Bit 7 - Reserved */
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#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4)
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#define CKGR_MOR_MOSCRCEN (0x01 << 3)
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/* Bit 2 - Reserved */
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#define CKGR_MOR_MOSCXTBY (0x01 << 1)
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#define CKGR_MOR_MOSCXTEN (0x01 << 0)
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/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */
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#define CKGR_PLLAR_ONE (0x01 << 29)
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#define CKGR_PLLAR_MULA_MASK (0x7FF << 16)
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#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8)
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#define CKGR_PLLAR_DIVA_MASK (0xFF << 0)
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/* PMC Master Clock Register (PMC_MCKR) */
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/* Bit [31:14] - Reserved */
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#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
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#define PMC_MCKR_PLLADIV2 (0x01 << 12)
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/* Bit [11:7] - Reserved */
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#define PMC_MCKR_PRES_MASK (0x07 << 4)
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/* Bit [3:2] - Reserved */
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#define PMC_MCKR_CSS_MASK (0x03 << 0)
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#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0)
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#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0)
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#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0)
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#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0)
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/* PMC USB Clock Register (PMC_USB) */
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/* Bit [31:12] - Reserved */
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#define PMC_USB_USBDIV_MASK (0x0F << 8)
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/* Bit [7:1] - Reserved */
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#define PMC_USB_USBS (0x01 << 0)
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/* PMC Status Register (PMC_SR) */
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/* Bits [31:21] - Reserved */
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#define PMC_SR_FOS (0x01 << 20)
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#define PMC_SR_CFDS (0x01 << 19)
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#define PMC_SR_CFDEV (0x01 << 18)
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#define PMC_SR_MOSCRCS (0x01 << 17)
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#define PMC_SR_MOSCSELS (0x01 << 16)
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/* Bits [15:11] - Reserved */
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#define PMC_SR_PCKRDY2 (0x01 << 10)
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#define PMC_SR_PCKRDY1 (0x01 << 9)
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#define PMC_SR_PCKRDY0 (0x01 << 8)
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#define PMC_SR_OSCSELS (0x01 << 7)
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#define PMC_SR_LOCKU (0x01 << 6)
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/* Bits [5:4] - Reserved */
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#define PMC_SR_MCKRDY (0x01 << 3)
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/* Bit [2] - Reserved */
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#define PMC_SR_LOCKA (0x01 << 1)
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#define PMC_SR_MOSCXTS (0x01 << 0)
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extern u32 pmc_mck_frequency;
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enum mck_src {
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MCK_SRC_SLOW = 0,
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MCK_SRC_MAIN = 1,
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MCK_SRC_PLLA = 2,
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MCK_SRC_UPLL = 3,
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};
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void pmc_mck_set_source(enum mck_src src);
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void pmc_xtal_enable(bool en, u8 startup_time);
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void pmc_plla_config(u8 mul, u8 div);
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void pmc_peripheral_clock_enable(u8 pid);
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void pmc_peripheral_clock_disable(u8 pid);
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void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
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#endif
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