546 lines
12 KiB
C
546 lines
12 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopenstm32/dma.h>
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void dma_enable_mem2mem_mode(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM;
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DMA_CCR1(dma) &= ~DMA_CCR1_CIRC;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_MEM2MEM;
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DMA_CCR2(dma) &= ~DMA_CCR2_CIRC;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_MEM2MEM;
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DMA_CCR3(dma) &= ~DMA_CCR3_CIRC;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_MEM2MEM;
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DMA_CCR4(dma) &= ~DMA_CCR4_CIRC;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_MEM2MEM;
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DMA_CCR5(dma) &= ~DMA_CCR5_CIRC;
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case 6:
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if (dma == DMA1) {
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DMA_CCR6(dma) |= DMA_CCR6_MEM2MEM;
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DMA_CCR6(dma) &= ~DMA_CCR6_CIRC;
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}
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case 7:
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if (dma == DMA1) {
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DMA_CCR7(dma) |= DMA_CCR7_MEM2MEM;
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DMA_CCR7(dma) &= ~DMA_CCR7_CIRC;
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}
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}
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}
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void dma_set_priority(u32 dma, u8 channel, u8 prio)
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{
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/* parameter check */
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if (prio > 3)
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return;
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB);
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DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB);
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case 2:
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DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PL_LSB);
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DMA_CCR2(dma) |= (prio << DMA_CCR2_PL_LSB);
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case 3:
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DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PL_LSB);
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DMA_CCR3(dma) |= (prio << DMA_CCR3_PL_LSB);
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case 4:
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DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PL_LSB);
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DMA_CCR4(dma) |= (prio << DMA_CCR4_PL_LSB);
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case 5:
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DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PL_LSB);
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DMA_CCR5(dma) |= (prio << DMA_CCR5_PL_LSB);
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case 6:
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if (dma == DMA1) {
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DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PL_LSB);
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DMA_CCR6(dma) |= (prio << DMA_CCR6_PL_LSB);
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}
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case 7:
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if (dma == DMA1) {
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DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PL_LSB);
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DMA_CCR7(dma) |= (prio << DMA_CCR7_PL_LSB);
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}
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}
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}
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void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size)
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{
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/* parameter check */
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if (mem_size > 2)
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return;
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB);
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DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB);
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case 2:
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DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_MSIZE_LSB);
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DMA_CCR2(dma) |= (mem_size << DMA_CCR2_MSIZE_LSB);
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case 3:
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DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_MSIZE_LSB);
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DMA_CCR3(dma) |= (mem_size << DMA_CCR3_MSIZE_LSB);
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case 4:
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DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_MSIZE_LSB);
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DMA_CCR4(dma) |= (mem_size << DMA_CCR4_MSIZE_LSB);
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case 5:
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DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_MSIZE_LSB);
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DMA_CCR5(dma) |= (mem_size << DMA_CCR5_MSIZE_LSB);
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case 6:
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if (dma == DMA1) {
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DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_MSIZE_LSB);
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DMA_CCR6(dma) |= (mem_size << DMA_CCR6_MSIZE_LSB);
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}
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case 7:
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if (dma == DMA1) {
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DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_MSIZE_LSB);
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DMA_CCR7(dma) |= (mem_size << DMA_CCR7_MSIZE_LSB);
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}
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}
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}
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void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size)
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{
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/* parameter check */
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if (peripheral_size > 2)
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return;
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB);
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DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB);
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case 2:
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DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PSIZE_LSB);
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DMA_CCR2(dma) |= (peripheral_size << DMA_CCR2_PSIZE_LSB);
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case 3:
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DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PSIZE_LSB);
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DMA_CCR3(dma) |= (peripheral_size << DMA_CCR3_PSIZE_LSB);
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case 4:
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DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PSIZE_LSB);
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DMA_CCR4(dma) |= (peripheral_size << DMA_CCR4_PSIZE_LSB);
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case 5:
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DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PSIZE_LSB);
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DMA_CCR5(dma) |= (peripheral_size << DMA_CCR5_PSIZE_LSB);
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case 6:
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if (dma == DMA1) {
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DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB);
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DMA_CCR6(dma) |= (peripheral_size << DMA_CCR6_PSIZE_LSB);
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}
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case 7:
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if (dma == DMA1) {
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DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB);
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DMA_CCR7(dma) |= (peripheral_size << DMA_CCR7_PSIZE_LSB);
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}
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}
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}
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void dma_enable_memory_increment_mode(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_MINC;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_MINC;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_MINC;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_MINC;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_MINC;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_MINC;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_MINC;
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}
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}
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void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_PINC;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_PINC;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_PINC;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_PINC;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_PINC;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_PINC;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_PINC;
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}
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}
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void dma_enable_circular_mode(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_CIRC;
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DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_CIRC;
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DMA_CCR2(dma) &= ~DMA_CCR2_MEM2MEM;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_CIRC;
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DMA_CCR3(dma) &= ~DMA_CCR3_MEM2MEM;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_CIRC;
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DMA_CCR4(dma) &= ~DMA_CCR4_MEM2MEM;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_CIRC;
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DMA_CCR5(dma) &= ~DMA_CCR5_MEM2MEM;
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case 6:
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if (dma == DMA1) {
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DMA_CCR6(dma) |= DMA_CCR6_CIRC;
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DMA_CCR6(dma) &= ~DMA_CCR6_MEM2MEM;
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}
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case 7:
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if (dma == DMA1) {
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DMA_CCR7(dma) |= DMA_CCR7_CIRC;
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DMA_CCR7(dma) &= ~DMA_CCR7_MEM2MEM;
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}
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}
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}
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void dma_set_read_from_peripheral(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~DMA_CCR1_DIR;
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case 2:
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DMA_CCR2(dma) &= ~DMA_CCR2_DIR;
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case 3:
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DMA_CCR3(dma) &= ~DMA_CCR3_DIR;
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case 4:
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DMA_CCR4(dma) &= ~DMA_CCR4_DIR;
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case 5:
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DMA_CCR5(dma) &= ~DMA_CCR5_DIR;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) &= ~DMA_CCR6_DIR;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) &= ~DMA_CCR7_DIR;
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}
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}
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void dma_set_read_from_memory(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_DIR;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_DIR;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_DIR;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_DIR;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_DIR;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_DIR;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_DIR;
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}
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}
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void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_TEIE;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_TEIE;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_TEIE;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_TEIE;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_TEIE;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_TEIE;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_TEIE;
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}
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}
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void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~DMA_CCR1_TEIE;
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case 2:
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DMA_CCR2(dma) &= ~DMA_CCR2_TEIE;
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case 3:
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DMA_CCR3(dma) &= ~DMA_CCR3_TEIE;
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case 4:
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DMA_CCR4(dma) &= ~DMA_CCR4_TEIE;
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case 5:
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DMA_CCR5(dma) &= ~DMA_CCR5_TEIE;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) &= ~DMA_CCR6_TEIE;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) &= ~DMA_CCR7_TEIE;
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}
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}
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void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_HTIE;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_HTIE;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_HTIE;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_HTIE;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_HTIE;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_HTIE;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_HTIE;
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}
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}
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void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~DMA_CCR1_HTIE;
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case 2:
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DMA_CCR2(dma) &= ~DMA_CCR2_HTIE;
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case 3:
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DMA_CCR3(dma) &= ~DMA_CCR3_HTIE;
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case 4:
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DMA_CCR4(dma) &= ~DMA_CCR4_HTIE;
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case 5:
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DMA_CCR5(dma) &= ~DMA_CCR5_HTIE;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) &= ~DMA_CCR6_HTIE;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) &= ~DMA_CCR7_HTIE;
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}
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}
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void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_TCIE;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_TCIE;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_TCIE;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_TCIE;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_TCIE;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_TCIE;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_TCIE;
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}
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}
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void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~DMA_CCR1_TCIE;
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case 2:
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DMA_CCR2(dma) &= ~DMA_CCR2_TCIE;
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case 3:
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DMA_CCR3(dma) &= ~DMA_CCR3_TCIE;
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case 4:
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DMA_CCR4(dma) &= ~DMA_CCR4_TCIE;
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case 5:
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DMA_CCR5(dma) &= ~DMA_CCR5_TCIE;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) &= ~DMA_CCR6_TCIE;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) &= ~DMA_CCR7_TCIE;
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}
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}
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void dma_enable_channel(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) |= DMA_CCR1_EN;
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case 2:
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DMA_CCR2(dma) |= DMA_CCR2_EN;
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case 3:
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DMA_CCR3(dma) |= DMA_CCR3_EN;
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case 4:
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DMA_CCR4(dma) |= DMA_CCR4_EN;
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case 5:
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DMA_CCR5(dma) |= DMA_CCR5_EN;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) |= DMA_CCR6_EN;
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case 7:
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if (dma == DMA1)
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DMA_CCR7(dma) |= DMA_CCR7_EN;
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}
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}
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void dma_disable_channel(u32 dma, u8 channel)
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{
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switch (channel)
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{
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case 1:
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DMA_CCR1(dma) &= ~DMA_CCR1_EN;
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case 2:
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DMA_CCR2(dma) &= ~DMA_CCR2_EN;
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case 3:
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DMA_CCR3(dma) &= ~DMA_CCR3_EN;
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case 4:
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DMA_CCR4(dma) &= ~DMA_CCR4_EN;
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case 5:
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DMA_CCR5(dma) &= ~DMA_CCR5_EN;
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case 6:
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if (dma == DMA1)
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DMA_CCR6(dma) &= ~DMA_CCR6_EN;
|
|
case 7:
|
|
if (dma == DMA1)
|
|
DMA_CCR7(dma) &= ~DMA_CCR7_EN;
|
|
}
|
|
}
|
|
|
|
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
|
|
{
|
|
switch (channel)
|
|
{
|
|
case 1:
|
|
DMA_CPAR1(dma) = (u32)address;
|
|
case 2:
|
|
DMA_CPAR2(dma) = (u32)address;
|
|
case 3:
|
|
DMA_CPAR3(dma) = (u32)address;
|
|
case 4:
|
|
DMA_CPAR4(dma) = (u32)address;
|
|
case 5:
|
|
DMA_CPAR5(dma) = (u32)address;
|
|
case 6:
|
|
if (dma == DMA1)
|
|
DMA_CPAR6(dma) = (u32)address;
|
|
case 7:
|
|
if (dma == DMA1)
|
|
DMA_CPAR7(dma) = (u32)address;
|
|
}
|
|
}
|
|
|
|
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
|
|
{
|
|
switch (channel)
|
|
{
|
|
case 1:
|
|
DMA_CMAR1(dma) = (u32)address;
|
|
case 2:
|
|
DMA_CMAR2(dma) = (u32)address;
|
|
case 3:
|
|
DMA_CMAR3(dma) = (u32)address;
|
|
case 4:
|
|
DMA_CMAR4(dma) = (u32)address;
|
|
case 5:
|
|
DMA_CMAR5(dma) = (u32)address;
|
|
case 6:
|
|
if (dma == DMA1)
|
|
DMA_CMAR6(dma) = (u32)address;
|
|
case 7:
|
|
if (dma == DMA1)
|
|
DMA_CMAR7(dma) = (u32)address;
|
|
}
|
|
}
|
|
|
|
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
|
|
{
|
|
switch (channel)
|
|
{
|
|
case 1:
|
|
DMA_CNDTR1(dma) = number;
|
|
case 2:
|
|
DMA_CNDTR2(dma) = number;
|
|
case 3:
|
|
DMA_CNDTR3(dma) = number;
|
|
case 4:
|
|
DMA_CNDTR4(dma) = number;
|
|
case 5:
|
|
DMA_CNDTR5(dma) = number;
|
|
case 6:
|
|
if (dma == DMA1)
|
|
DMA_CNDTR6(dma) = number;
|
|
case 7:
|
|
if (dma == DMA1)
|
|
DMA_CNDTR7(dma) = number;
|
|
}
|
|
}
|
|
|
|
|