301 lines
8.7 KiB
C
301 lines
8.7 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_USART_H
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#define LIBOPENSTM32_USART_H
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#include <libopenstm32/memorymap.h>
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#include <libopenstm32/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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#define USART1 USART1_BASE
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#define USART2 USART2_BASE
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#define USART3 USART3_BASE
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#define UART4 UART4_BASE
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#define UART5 UART5_BASE
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/* --- USART registers ----------------------------------------------------- */
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/* Status register (USARTx_SR) */
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#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
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#define USART1_SR USART_SR(USART1_BASE)
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#define USART2_SR USART_SR(USART2_BASE)
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#define USART3_SR USART_SR(USART3_BASE)
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#define UART4_SR USART_SR(UART4_BASE)
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#define UART5_SR USART_SR(UART5_BASE)
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/* Data register (USARTx_DR) */
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#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
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#define USART1_DR USART_DR(USART1_BASE)
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#define USART2_DR USART_DR(USART2_BASE)
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#define USART3_DR USART_DR(USART3_BASE)
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#define UART4_DR USART_DR(UART4_BASE)
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#define UART5_DR USART_DR(UART5_BASE)
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/* Baud rate register (USARTx_BRR) */
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#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
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#define USART1_BRR USART_BRR(USART1_BASE)
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#define USART2_BRR USART_BRR(USART2_BASE)
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#define USART3_BRR USART_BRR(USART3_BASE)
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#define UART4_BRR USART_BRR(UART4_BASE)
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#define UART5_BRR USART_BRR(UART5_BASE)
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/* Control register 1 (USARTx_CR1) */
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#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
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#define USART1_CR1 USART_CR1(USART1_BASE)
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#define USART2_CR1 USART_CR1(USART2_BASE)
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#define USART3_CR1 USART_CR1(USART3_BASE)
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#define UART4_CR1 USART_CR1(UART4_BASE)
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#define UART5_CR1 USART_CR1(UART5_BASE)
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/* Control register 2 (USARTx_CR2) */
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#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
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#define USART1_CR2 USART_CR2(USART1_BASE)
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#define USART2_CR2 USART_CR2(USART2_BASE)
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#define USART3_CR2 USART_CR2(USART3_BASE)
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#define UART4_CR2 USART_CR2(UART4_BASE)
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#define UART5_CR2 USART_CR2(UART5_BASE)
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/* Control register 3 (USARTx_CR3) */
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#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
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#define USART1_CR3 USART_CR3(USART1_BASE)
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#define USART2_CR3 USART_CR3(USART2_BASE)
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#define USART3_CR3 USART_CR3(USART3_BASE)
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#define UART4_CR3 USART_CR3(UART4_BASE)
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#define UART5_CR3 USART_CR3(UART5_BASE)
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/* Guard time and prescaler register (USARTx_GTPR) */
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#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
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#define USART1_GTPR USART_GTPR(USART1_BASE)
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#define USART2_GTPR USART_GTPR(USART2_BASE)
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#define USART3_GTPR USART_GTPR(USART3_BASE)
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#define UART4_GTPR USART_GTPR(UART4_BASE)
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#define UART5_GTPR USART_GTPR(UART5_BASE)
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/* --- USART_SR values ----------------------------------------------------- */
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/* CTS: CTS flag */
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/* Note: N/A on UART4/5 */
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#define USART_SR_CTS (1 << 9)
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/* LBD: LIN break detection flag */
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#define USART_SR_LBD (1 << 8)
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/* TXE: Transmit data buffer empty */
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#define USART_SR_TXE (1 << 7)
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/* TC: Transmission complete */
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#define USART_SR_TC (1 << 6)
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/* RXNE: Read data register not empty */
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#define USART_SR_RXNE (1 << 5)
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/* IDLE: Idle line detected */
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#define USART_SR_IDLE (1 << 4)
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/* ORE: Overrun error */
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#define USART_SR_ORE (1 << 3)
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/* NE: Noise error flag */
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#define USART_SR_NE (1 << 2)
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/* FE: Framing error */
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#define USART_SR_FE (1 << 1)
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/* PE: Parity error */
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#define USART_SR_PE (1 << 0)
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/* --- USART_DR values ----------------------------------------------------- */
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/* USART_DR[8:0]: DR[8:0]: Data value */
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#define USART_DR_MASK 0xFF
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/* --- USART_BRR values ---------------------------------------------------- */
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/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
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#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
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/* DIV_Fraction[3:0]: fraction of USARTDIV */
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#define USART_BRR_DIV_FRACTION_MASK 0xF
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/* --- USART_CR1 values ---------------------------------------------------- */
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/* UE: USART enable */
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#define USART_CR1_UE (1 << 13)
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/* M: Word length */
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#define USART_CR1_M (1 << 12)
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/* WAKE: Wakeup method */
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#define USART_CR1_WAKE (1 << 11)
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/* PCE: Parity control enable */
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#define USART_CR1_PCE (1 << 10)
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/* PS: Parity selection */
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#define USART_CR1_PS (1 << 9)
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/* PEIE: PE interrupt enable */
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#define USART_CR1_PEIE (1 << 8)
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/* TXEIE: TXE interrupt enable */
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#define USART_CR1_TXEIE (1 << 7)
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/* TCIE: Transmission complete interrupt enable */
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#define USART_CR1_TCIE (1 << 6)
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/* RXNEIE: RXNE interrupt enable */
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#define USART_CR1_RXNEIE (1 << 5)
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/* IDLEIE: IDLE interrupt enable */
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#define USART_CR1_IDLEIE (1 << 4)
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/* TE: Transmitter enable */
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#define USART_CR1_TE (1 << 3)
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/* RE: Receiver enable */
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#define USART_CR1_RE (1 << 2)
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/* RWU: Receiver wakeup */
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#define USART_CR1_RWU (1 << 1)
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/* SBK: Send break */
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#define USART_CR1_SBK (1 << 0)
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/* CR1_PCE / CR1_PS combined values */
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#define USART_PARITY_NONE 0x00
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#define USART_PARITY_ODD 0x02
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#define USART_PARITY_EVEN 0x03
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/* CR1_TE/CR1_RE combined values */
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#define USART_MODE_RX 0x01
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#define USART_MODE_TX 0x02
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#define USART_MODE_TX_RX 0x03
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/* --- USART_CR2 values ---------------------------------------------------- */
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/* LINEN: LIN mode enable */
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#define USART_CR2_LINEN (1 << 14)
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/* STOP[13:12]: STOP bits */
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#define USART_STOPBITS_1 0x00 /* 1 stop bit */
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#define USART_STOPBITS_0_5 0x01 /* 0.5 stop bits */
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#define USART_STOPBITS_2 0x02 /* 2 stop bits */
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#define USART_STOPBITS_1_5 0x03 /* 1.5 stop bits */
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/* CLKEN: Clock enable */
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#define USART_CR2_CLKEN (1 << 11)
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/* CPOL: Clock polarity */
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#define USART_CR2_CPOL (1 << 10)
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/* CPHA: Clock phase */
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#define USART_CR2_CPHA (1 << 9)
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/* LBCL: Last bit clock pulse */
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#define USART_CR2_LBCL (1 << 8)
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/* LBDIE: LIN break detection interrupt enable */
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#define USART_CR2_LBDIE (1 << 6)
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/* LBDL: LIN break detection length */
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#define USART_CR2_LBDL (1 << 5)
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/* ADD[3:0]: Addres of the usart node */
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#define USART_CR2_ADD_MASK 0xF
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/* --- USART_CR3 values ---------------------------------------------------- */
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/* CTSIE: CTS interrupt enable */
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/* Note: N/A on UART4 & UART5 */
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#define USART_CR3_CTSIE (1 << 10)
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/* CTSE: CTS enable */
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/* Note: N/A on UART4 & UART5 */
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#define USART_CR3_CTSE (1 << 9)
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/* RTSE: RTS enable */
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/* Note: N/A on UART4 & UART5 */
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#define USART_CR3_RTSE (1 << 8)
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/* DMAT: DMA enable transmitter */
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/* Note: N/A on UART5 */
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#define USART_CR3_DMAT (1 << 7)
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/* DMAR: DMA enable receiver */
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/* Note: N/A on UART5 */
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#define USART_CR3_DMAR (1 << 6)
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/* SCEN: Smartcard mode enable */
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/* Note: N/A on UART4 & UART5 */
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#define USART_CR3_SCEN (1 << 5)
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/* NACK: Smartcard NACK enable */
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/* Note: N/A on UART4 & UART5 */
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#define USART_CR3_NACK (1 << 4)
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/* HDSEL: Half-duplex selection */
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#define USART_CR3_HDSEL (1 << 3)
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/* IRLP: IrDA low-power */
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#define USART_CR3_IRLP (1 << 2)
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/* IREN: IrDA mode enable */
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#define USART_CR3_IREN (1 << 1)
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/* EIE: Error interrupt enable */
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#define USART_CR3_EIE (1 << 0)
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/* CR3_CTSE/CR3_RTSE combined values */
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#define USART_FLOWCONTROL_NONE 0x00
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#define USART_FLOWCONTROL_RTS 0x01
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#define USART_FLOWCONTROL_CTS 0x02
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#define USART_FLOWCONTROL_RTS_CTS 0x03
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/* --- USART_GTPR values --------------------------------------------------- */
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/* GT[7:0]: Guard time value */
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/* Note: N/A on UART4 & UART5 */
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#define USART_GTPR_GT_MASK (0xFF << 8)
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/* PSC[7:0]: Prescaler value */
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/* Note: N/A on UART4/5 */
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#define USART_GTPR_PSC_MASK 0xFF
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/* TODO */ /* Note to Uwe: what needs to be done here? */
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/* --- Function prototypes ------------------------------------------------- */
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void usart_set_baudrate(u32 usart, u32 baud);
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void usart_set_databits(u32 usart, u32 bits);
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void usart_set_stopbits(u32 usart, u32 stopbits);
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void usart_set_parity(u32 usart, u32 parity);
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void usart_set_mode(u32 usart, u32 mode);
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void usart_set_flow_control(u32 usart, u32 flowcontrol);
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void usart_enable(u32 usart);
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void usart_disable(u32 usart);
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void usart_send(u32 usart, u16 data);
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u16 usart_recv(u32 usart);
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void usart_wait_send_ready(u32 usart);
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void usart_wait_recv_ready(u32 usart);
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void usart_send_blocking(u32 usart, u16 data);
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u16 usart_recv_blocking(u32 usart);
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#endif
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