683 lines
15 KiB
C
683 lines
15 KiB
C
/** @defgroup rcc_file RCC
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*
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* @ingroup STM32F4xx
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*
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* @section rcc_f4_api_ex Reset and Clock Control API.
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*
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* @brief <b>libopencm3 STM32F4xx Reset and Clock Control</b>
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*
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* @author @htmlonly © @endhtmlonly 2013 Frantisek Burian <BuFran at seznam.cz>
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*
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* @date 18 Jun 2013
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*
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* This library supports the Reset and Clock Control System in the STM32 series
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* of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/flash.h>
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/**@{*/
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 16000000;
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uint32_t rcc_apb1_frequency = 16000000;
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uint32_t rcc_apb2_frequency = 16000000;
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const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 8,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 84MHz */
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.pllm = 8,
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.plln = 336,
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.pllp = 4,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 120MHz */
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.pllm = 8,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 8,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 12,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 84MHz */
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.pllm = 12,
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.plln = 336,
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.pllp = 4,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 120MHz */
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.pllm = 12,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 12,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 16,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 84MHz */
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.pllm = 16,
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.plln = 336,
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.pllp = 4,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 120MHz */
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.pllm = 16,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 16,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 25,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 84MHz */
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.pllm = 25,
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.plln = 336,
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.pllp = 4,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 120MHz */
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.pllm = 25,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 25,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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case RCC_PLLSAI:
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RCC_CIR |= RCC_CIR_PLLSAIRDYC;
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break;
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case RCC_PLLI2S:
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RCC_CIR |= RCC_CIR_PLLI2SRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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case RCC_PLLSAI:
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RCC_CIR |= RCC_CIR_PLLSAIRDYIE;
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break;
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case RCC_PLLI2S:
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RCC_CIR |= RCC_CIR_PLLI2SRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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case RCC_PLLSAI:
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RCC_CIR &= ~RCC_CIR_PLLSAIRDYIE;
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break;
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case RCC_PLLI2S:
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RCC_CIR &= ~RCC_CIR_PLLI2SRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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case RCC_HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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case RCC_HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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case RCC_LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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case RCC_LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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case RCC_PLLSAI:
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return ((RCC_CIR & RCC_CIR_PLLSAIRDYF) != 0);
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case RCC_PLLI2S:
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return ((RCC_CIR & RCC_CIR_PLLI2SRDYF) != 0);
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}
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return 0;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case RCC_HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case RCC_HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case RCC_LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case RCC_LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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case RCC_PLLSAI:
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while ((RCC_CR & RCC_CR_PLLSAIRDY) == 0);
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break;
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case RCC_PLLI2S:
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while ((RCC_CR & RCC_CR_PLLI2SRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_PLL);
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break;
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case RCC_HSE:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_HSE);
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break;
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case RCC_HSI:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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case RCC_PLLSAI:
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RCC_CR |= RCC_CR_PLLSAION;
|
|
break;
|
|
case RCC_PLLI2S:
|
|
RCC_CR |= RCC_CR_PLLI2SON;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void rcc_osc_off(enum rcc_osc osc)
|
|
{
|
|
switch (osc) {
|
|
case RCC_PLL:
|
|
RCC_CR &= ~RCC_CR_PLLON;
|
|
break;
|
|
case RCC_HSE:
|
|
RCC_CR &= ~RCC_CR_HSEON;
|
|
break;
|
|
case RCC_HSI:
|
|
RCC_CR &= ~RCC_CR_HSION;
|
|
break;
|
|
case RCC_LSE:
|
|
RCC_BDCR &= ~RCC_BDCR_LSEON;
|
|
break;
|
|
case RCC_LSI:
|
|
RCC_CSR &= ~RCC_CSR_LSION;
|
|
break;
|
|
case RCC_PLLSAI:
|
|
RCC_CR &= ~RCC_CR_PLLSAION;
|
|
break;
|
|
case RCC_PLLI2S:
|
|
RCC_CR &= ~RCC_CR_PLLI2SON;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void rcc_css_enable(void)
|
|
{
|
|
RCC_CR |= RCC_CR_CSSON;
|
|
}
|
|
|
|
void rcc_css_disable(void)
|
|
{
|
|
RCC_CR &= ~RCC_CR_CSSON;
|
|
}
|
|
|
|
void rcc_osc_bypass_enable(enum rcc_osc osc)
|
|
{
|
|
switch (osc) {
|
|
case RCC_HSE:
|
|
RCC_CR |= RCC_CR_HSEBYP;
|
|
break;
|
|
case RCC_LSE:
|
|
RCC_BDCR |= RCC_BDCR_LSEBYP;
|
|
break;
|
|
default:
|
|
/* Do nothing, only HSE/LSE allowed here. */
|
|
break;
|
|
}
|
|
}
|
|
|
|
void rcc_osc_bypass_disable(enum rcc_osc osc)
|
|
{
|
|
switch (osc) {
|
|
case RCC_HSE:
|
|
RCC_CR &= ~RCC_CR_HSEBYP;
|
|
break;
|
|
case RCC_LSE:
|
|
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
|
|
break;
|
|
default:
|
|
/* Do nothing, only HSE/LSE allowed here. */
|
|
break;
|
|
}
|
|
}
|
|
|
|
void rcc_set_sysclk_source(uint32_t clk)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
reg32 = RCC_CFGR;
|
|
reg32 &= ~((1 << 1) | (1 << 0));
|
|
RCC_CFGR = (reg32 | clk);
|
|
}
|
|
|
|
void rcc_set_pll_source(uint32_t pllsrc)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
reg32 = RCC_PLLCFGR;
|
|
reg32 &= ~(1 << 22);
|
|
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
|
|
}
|
|
|
|
void rcc_set_ppre2(uint32_t ppre2)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
reg32 = RCC_CFGR;
|
|
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
|
|
RCC_CFGR = (reg32 | (ppre2 << 13));
|
|
}
|
|
|
|
void rcc_set_ppre1(uint32_t ppre1)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
reg32 = RCC_CFGR;
|
|
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
|
|
RCC_CFGR = (reg32 | (ppre1 << 10));
|
|
}
|
|
|
|
void rcc_set_hpre(uint32_t hpre)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
reg32 = RCC_CFGR;
|
|
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
|
|
RCC_CFGR = (reg32 | (hpre << 4));
|
|
}
|
|
|
|
void rcc_set_rtcpre(uint32_t rtcpre)
|
|
{
|
|
uint32_t reg32;
|
|
|
|
reg32 = RCC_CFGR;
|
|
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
|
|
RCC_CFGR = (reg32 | (rtcpre << 16));
|
|
}
|
|
|
|
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
|
|
uint32_t pllq)
|
|
{
|
|
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
|
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
|
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
|
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
|
}
|
|
|
|
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
|
|
uint32_t pllq)
|
|
{
|
|
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
|
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
|
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
|
RCC_PLLCFGR_PLLSRC |
|
|
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
|
}
|
|
|
|
uint32_t rcc_system_clock_source(void)
|
|
{
|
|
/* Return the clock source which is used as system clock. */
|
|
return (RCC_CFGR & 0x000c) >> 2;
|
|
}
|
|
|
|
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
|
|
{
|
|
/* Enable internal high-speed oscillator. */
|
|
rcc_osc_on(RCC_HSI);
|
|
rcc_wait_for_osc_ready(RCC_HSI);
|
|
|
|
/* Select HSI as SYSCLK source. */
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
|
|
|
/* Enable external high-speed oscillator 8MHz. */
|
|
rcc_osc_on(RCC_HSE);
|
|
rcc_wait_for_osc_ready(RCC_HSE);
|
|
|
|
/* Enable/disable high performance mode */
|
|
if (!clock->power_save) {
|
|
pwr_set_vos_scale(PWR_SCALE1);
|
|
} else {
|
|
pwr_set_vos_scale(PWR_SCALE2);
|
|
}
|
|
|
|
/*
|
|
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
|
* Do this before touching the PLL (TODO: why?).
|
|
*/
|
|
rcc_set_hpre(clock->hpre);
|
|
rcc_set_ppre1(clock->ppre1);
|
|
rcc_set_ppre2(clock->ppre2);
|
|
|
|
rcc_set_main_pll_hse(clock->pllm, clock->plln,
|
|
clock->pllp, clock->pllq);
|
|
|
|
/* Enable PLL oscillator and wait for it to stabilize. */
|
|
rcc_osc_on(RCC_PLL);
|
|
rcc_wait_for_osc_ready(RCC_PLL);
|
|
|
|
/* Configure flash settings. */
|
|
flash_set_ws(clock->flash_config);
|
|
|
|
/* Select PLL as SYSCLK source. */
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
|
|
|
/* Wait for PLL clock to be selected. */
|
|
rcc_wait_for_sysclk_status(RCC_PLL);
|
|
|
|
/* Set the peripheral clock frequencies used. */
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
|
rcc_apb1_frequency = clock->apb1_frequency;
|
|
rcc_apb2_frequency = clock->apb2_frequency;
|
|
|
|
/* Disable internal high-speed oscillator. */
|
|
rcc_osc_off(RCC_HSI);
|
|
}
|
|
|
|
/**@}*/
|