390 lines
10 KiB
C
390 lines
10 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/tools.h>
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#include <libopencm3/stm32/otg_fs.h>
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#include <libopencm3/usb/usbd.h>
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#include "usb_private.h"
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/* Receive FIFO size in 32-bit words. */
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#define RX_FIFO_SIZE 128
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static uint16_t fifo_mem_top;
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static uint16_t fifo_mem_top_ep0;
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static u8 force_nak[4];
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static void stm32f107_usbd_init(void);
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static void stm32f107_set_address(u8 addr);
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static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
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void (*callback)(u8 ep));
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static void stm32f107_endpoints_reset(void);
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static void stm32f107_ep_stall_set(u8 addr, u8 stall);
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static u8 stm32f107_ep_stall_get(u8 addr);
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static void stm32f107_ep_nak_set(u8 addr, u8 nak);
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static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len);
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static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len);
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static void stm32f107_poll(void);
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static void stm32f107_disconnect(bool disconnected);
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/*
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* We keep a backup copy of the out endpoint size registers to restore them
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* after a transaction.
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*/
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static u32 doeptsiz[4];
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const struct _usbd_driver stm32f107_usb_driver = {
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.init = stm32f107_usbd_init,
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.set_address = stm32f107_set_address,
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.ep_setup = stm32f107_ep_setup,
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.ep_reset = stm32f107_endpoints_reset,
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.ep_stall_set = stm32f107_ep_stall_set,
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.ep_stall_get = stm32f107_ep_stall_get,
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.ep_nak_set = stm32f107_ep_nak_set,
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.ep_write_packet = stm32f107_ep_write_packet,
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.ep_read_packet = stm32f107_ep_read_packet,
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.poll = stm32f107_poll,
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.disconnect = stm32f107_disconnect,
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};
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/** Initialize the USB device controller hardware of the STM32. */
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static void stm32f107_usbd_init(void)
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{
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OTG_FS_GINTSTS = OTG_FS_GINTSTS_MMIS;
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OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_PHYSEL;
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/* Enable VBUS sensing in device mode and power down the PHY. */
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OTG_FS_GCCFG |= OTG_FS_GCCFG_VBUSBSEN | OTG_FS_GCCFG_PWRDWN;
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/* Wait for AHB idle. */
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while (!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL)) ;
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/* Do core soft reset. */
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OTG_FS_GRSTCTL |= OTG_FS_GRSTCTL_CSRST;
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while (OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST) ;
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/* Force peripheral only mode. */
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OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_FDMOD | OTG_FS_GUSBCFG_TRDT_MASK;
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/* Full speed device. */
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OTG_FS_DCFG |= OTG_FS_DCFG_DSPD;
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/* Restart the PHY clock. */
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OTG_FS_PCGCCTL = 0;
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OTG_FS_GRXFSIZ = RX_FIFO_SIZE;
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fifo_mem_top = RX_FIFO_SIZE;
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/* Unmask interrupts for TX and RX. */
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OTG_FS_GAHBCFG |= OTG_FS_GAHBCFG_GINT;
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OTG_FS_GINTMSK = OTG_FS_GINTMSK_ENUMDNEM |
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OTG_FS_GINTMSK_RXFLVLM |
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OTG_FS_GINTMSK_IEPINT |
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OTG_FS_GINTMSK_USBSUSPM |
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OTG_FS_GINTMSK_WUIM |
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OTG_FS_GINTMSK_SOFM;
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OTG_FS_DAINTMSK = 0xF;
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OTG_FS_DIEPMSK = OTG_FS_DIEPMSK_XFRCM;
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}
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static void stm32f107_set_address(u8 addr)
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{
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OTG_FS_DCFG = (OTG_FS_DCFG & ~OTG_FS_DCFG_DAD) | (addr << 4);
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}
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static void stm32f107_ep_setup(u8 addr, u8 type, u16 max_size,
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void (*callback) (u8 ep))
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{
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/*
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* Configure endpoint address and type. Allocate FIFO memory for
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* endpoint. Install callback funciton.
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*/
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u8 dir = addr & 0x80;
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addr &= 0x7f;
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if (addr == 0) { /* For the default control endpoint */
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/* Configure IN part. */
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if (max_size >= 64) {
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OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_64;
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} else if (max_size >= 32) {
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OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_32;
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} else if (max_size >= 16) {
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OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_16;
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} else {
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OTG_FS_DIEPCTL0 = OTG_FS_DIEPCTL0_MPSIZ_8;
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}
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OTG_FS_DIEPTSIZ0 = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
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OTG_FS_DIEPCTL0 |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
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/* Configure OUT part. */
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doeptsiz[0] = OTG_FS_DIEPSIZ0_STUPCNT_1 | (1 << 19) |
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(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
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OTG_FS_DOEPTSIZ(0) = doeptsiz[0];
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OTG_FS_DOEPCTL(0) |=
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OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
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OTG_FS_GNPTXFSIZ = ((max_size / 4) << 16) | RX_FIFO_SIZE;
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fifo_mem_top += max_size / 4;
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fifo_mem_top_ep0 = fifo_mem_top;
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return;
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}
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if (dir) {
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OTG_FS_DIEPTXF(addr) = ((max_size / 4) << 16) | fifo_mem_top;
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fifo_mem_top += max_size / 4;
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OTG_FS_DIEPTSIZ(addr) =
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(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
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OTG_FS_DIEPCTL(addr) |=
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OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK | (type << 18)
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| OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID
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| (addr << 22) | max_size;
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if (callback) {
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_usbd_device.
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user_callback_ctr[addr][USB_TRANSACTION_IN] =
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(void *)callback;
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}
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}
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if (!dir) {
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doeptsiz[addr] = (1 << 19) |
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(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
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OTG_FS_DOEPTSIZ(addr) = doeptsiz[addr];
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OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_EPENA |
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OTG_FS_DOEPCTL0_USBAEP | OTG_FS_DIEPCTL0_CNAK |
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OTG_FS_DOEPCTLX_SD0PID | (type << 18) | max_size;
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if (callback) {
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_usbd_device.
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user_callback_ctr[addr][USB_TRANSACTION_OUT] =
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(void *)callback;
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}
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}
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}
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static void stm32f107_endpoints_reset(void)
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{
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/* The core resets the endpoints automatically on reset. */
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fifo_mem_top = fifo_mem_top_ep0;
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}
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static void stm32f107_ep_stall_set(u8 addr, u8 stall)
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{
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if (addr == 0) {
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if (stall)
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OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_STALL;
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else
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OTG_FS_DIEPCTL(addr) &= ~OTG_FS_DIEPCTL0_STALL;
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}
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if (addr & 0x80) {
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addr &= 0x7F;
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if (stall) {
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OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_STALL;
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} else {
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OTG_FS_DIEPCTL(addr) &= ~OTG_FS_DIEPCTL0_STALL;
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OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTLX_SD0PID;
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}
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} else {
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if (stall) {
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OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_STALL;
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} else {
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OTG_FS_DOEPCTL(addr) &= ~OTG_FS_DOEPCTL0_STALL;
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OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTLX_SD0PID;
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}
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}
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}
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static u8 stm32f107_ep_stall_get(u8 addr)
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{
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/* Return non-zero if STALL set. */
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if (addr & 0x80)
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return
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(OTG_FS_DIEPCTL(addr & 0x7f) & OTG_FS_DIEPCTL0_STALL) ? 1 : 0;
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else
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return (OTG_FS_DOEPCTL(addr) & OTG_FS_DOEPCTL0_STALL) ? 1 : 0;
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}
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static void stm32f107_ep_nak_set(u8 addr, u8 nak)
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{
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/* It does not make sence to force NAK on IN endpoints. */
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if (addr & 0x80)
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return;
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force_nak[addr] = nak;
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if (nak)
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OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_SNAK;
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else
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OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_CNAK;
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}
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static u16 stm32f107_ep_write_packet(u8 addr, const void *buf, u16 len)
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{
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const u32 *buf32 = buf;
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int i;
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addr &= 0x7F;
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/* Return if endpoint is already enabled. */
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if (OTG_FS_DIEPTSIZ(addr) & OTG_FS_DIEPSIZ0_PKTCNT)
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return 0;
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/* Enable endpoint for transmission. */
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OTG_FS_DIEPTSIZ(addr) = (1 << 19) | len;
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OTG_FS_DIEPCTL(addr) |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_CNAK;
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/* Copy buffer to endpoint FIFO. */
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volatile u32 *fifo = OTG_FS_FIFO(addr);
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for (i = len; i > 0; i -= 4)
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*fifo++ = *buf32++;
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return len;
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}
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/*
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* Received packet size for each endpoint. This is assigned in
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* stm32f107_poll() which reads the packet status push register GRXSTSP
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* for use in stm32f107_ep_read_packet().
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*/
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static uint16_t rxbcnt;
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static u16 stm32f107_ep_read_packet(u8 addr, void *buf, u16 len)
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{
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int i;
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u32 *buf32 = buf;
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u32 extra;
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len = MIN(len, rxbcnt);
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rxbcnt -= len;
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volatile u32 *fifo = OTG_FS_FIFO(addr);
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for (i = len; i >= 4; i -= 4)
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*buf32++ = *fifo++;
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if (i) {
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extra = *fifo++;
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memcpy(buf32, &extra, i);
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}
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OTG_FS_DOEPTSIZ(addr) = doeptsiz[addr];
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OTG_FS_DOEPCTL(addr) |= OTG_FS_DOEPCTL0_EPENA |
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(force_nak[addr] ? OTG_FS_DOEPCTL0_SNAK : OTG_FS_DOEPCTL0_CNAK);
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return len;
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}
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static void stm32f107_poll(void)
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{
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/* Read interrupt status register. */
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u32 intsts = OTG_FS_GINTSTS;
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int i;
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if (intsts & OTG_FS_GINTSTS_ENUMDNE) {
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/* Handle USB RESET condition. */
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OTG_FS_GINTSTS = OTG_FS_GINTSTS_ENUMDNE;
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fifo_mem_top = RX_FIFO_SIZE;
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_usbd_reset();
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return;
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}
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/* Note: RX and TX handled differently in this device. */
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if (intsts & OTG_FS_GINTSTS_RXFLVL) {
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/* Receive FIFO non-empty. */
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u32 rxstsp = OTG_FS_GRXSTSP;
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u32 pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK;
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if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) &&
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(pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP))
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return;
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u8 ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK;
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u8 type;
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if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP)
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type = USB_TRANSACTION_SETUP;
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else
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type = USB_TRANSACTION_OUT;
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/* Save packet size for stm32f107_ep_read_packet(). */
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rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4;
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/*
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* FIXME: Why is a delay needed here?
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* This appears to fix a problem where the first 4 bytes
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* of the DATA OUT stage of a control transaction are lost.
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*/
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for (i = 0; i < 1000; i++)
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__asm__("nop");
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if (_usbd_device.user_callback_ctr[ep][type])
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_usbd_device.user_callback_ctr[ep][type] (ep);
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/* Discard unread packet data. */
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for (i = 0; i < rxbcnt; i += 4)
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(void)*OTG_FS_FIFO(ep);
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rxbcnt = 0;
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}
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/*
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* There is no global interrupt flag for transmit complete.
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* The XFRC bit must be checked in each OTG_FS_DIEPINT(x).
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*/
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for (i = 0; i < 4; i++) { /* Iterate over endpoints. */
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if (OTG_FS_DIEPINT(i) & OTG_FS_DIEPINTX_XFRC) {
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/* Transfer complete. */
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if (_usbd_device.
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user_callback_ctr[i][USB_TRANSACTION_IN]) {
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_usbd_device.
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user_callback_ctr[i][USB_TRANSACTION_IN](i);
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}
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OTG_FS_DIEPINT(i) = OTG_FS_DIEPINTX_XFRC;
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}
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}
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if (intsts & OTG_FS_GINTSTS_USBSUSP) {
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if (_usbd_device.user_callback_suspend)
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_usbd_device.user_callback_suspend();
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OTG_FS_GINTSTS = OTG_FS_GINTSTS_USBSUSP;
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}
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if (intsts & OTG_FS_GINTSTS_WKUPINT) {
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if (_usbd_device.user_callback_resume)
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_usbd_device.user_callback_resume();
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OTG_FS_GINTSTS = OTG_FS_GINTSTS_WKUPINT;
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}
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if (intsts & OTG_FS_GINTSTS_SOF) {
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if (_usbd_device.user_callback_sof)
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_usbd_device.user_callback_sof();
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OTG_FS_GINTSTS = OTG_FS_GINTSTS_SOF;
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}
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}
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static void stm32f107_disconnect(bool disconnected)
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{
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if (disconnected) {
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OTG_FS_DCTL |= OTG_FS_DCTL_SDIS;
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} else {
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OTG_FS_DCTL &= ~OTG_FS_DCTL_SDIS;
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}
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}
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