102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
/** @defgroup flash_defines FLASH Defines
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*
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* @ingroup STM32F7xx_defines
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*
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* @author @htmlonly © @endhtmlonly 2017
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* Matthew Lai <m@matthewlai.ca>
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* @author @htmlonly © @endhtmlonly 2010
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* Thomas Otto <tommi@viadmin.org>
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* @author @htmlonly © @endhtmlonly 2010
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* Mark Butler <mbutler@physics.otago.ac.nz>
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/common/flash_common_all.h>
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#include <libopencm3/stm32/common/flash_common_f.h>
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#include <libopencm3/stm32/common/flash_common_f24.h>
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/*
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* Differences between F7 and F4:
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* 1. icache and dcache are now combined into a unified ART cache. The CPU has
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* its own d/i-caches, but those are unrelated to this. They are on the
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* AXIM bus.
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* 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
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* erase sequence error).
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* 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG (
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* window watchdog).
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*/
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/**@{*/
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/* --- FLASH_ACR values ---------------------------------------------------- */
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/** @addtogroup flash_acr_values FLASH_ACR values
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* @ingroup flash_registers
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@{*/
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#define FLASH_ACR_ARTRST (1 << 11)
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#define FLASH_ACR_ARTEN (1 << 9)
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#define FLASH_ACR_PRFTEN (1 << 8)
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/*@}*/
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#define FLASH_SR_ERSERR (1 << 7)
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/* --- FLASH_OPTCR values -------------------------------------------------- */
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#define FLASH_OPTCR_IWDG_STOP (1 << 31)
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#define FLASH_OPTCR_IWDG_STDBY (1 << 30)
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#define FLASH_OPTCR_NWRP_SHIFT 16
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#define FLASH_OPTCR_NWRP_MASK 0xff
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#define FLASH_OPTCR_RDP_SHIFT 8
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#define FLASH_OPTCR_RDP_MASK 0xff
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#define FLASH_OPTCR_IWDG_SW (1 << 5)
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#define FLASH_OPTCR_WWDG_SW (1 << 4)
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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/* --- FLASH_OPTCR1 values ------------------------------------------------- */
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#define FLASH_OPTCR1_BOOT_ADD1_MASK 0xffff
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#define FLASH_OPTCR1_BOOT_ADD1_SHIFT 16
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#define FLASH_OPTCR1_BOOT_ADD0_MASK 0xffff
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#define FLASH_OPTCR1_BOOT_ADD0_SHIFT 0
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void flash_clear_erserr_flag(void);
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void flash_art_enable(void);
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void flash_art_reset(void);
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END_DECLS
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/**@}*/
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#endif
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