100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/*
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*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Utility functions for the SDRAM component of the FMC */
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#include <stdint.h>
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#include <libopencm3/stm32/fsmc.h>
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/*
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* Install various timing values into the correct place in the
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* SDRAM Timing Control Register format.
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*
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* Note that the register is 'zero' based to save bits so 1 cycle
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* is stored as '0'. This command takes actual cycles and adjusts
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* by subtracting 1.
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*/
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uint32_t
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sdram_timing(struct sdram_timing *t) {
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uint32_t result;
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result = 0;
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result |= ((t->trcd - 1) & 0xf) << FMC_SDTR_TRCD_SHIFT;
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result |= ((t->trp - 1) & 0xf) << FMC_SDTR_TRP_SHIFT;
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result |= ((t->twr - 1) & 0xf) << FMC_SDTR_TWR_SHIFT;
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result |= ((t->trc - 1) & 0xf) << FMC_SDTR_TRC_SHIFT;
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result |= ((t->tras - 1) & 0xf) << FMC_SDTR_TRAS_SHIFT;
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result |= ((t->txsr - 1) & 0xf) << FMC_SDTR_TXSR_SHIFT;
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result |= ((t->tmrd - 1) & 0xf) << FMC_SDTR_TMRD_SHIFT;
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return result;
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}
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/*
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* Send a command to the SDRAM controller, wait until it is not
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* busy before sending. This allows you to chain sending commands
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* and the code will pause as needed between them.
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*/
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void
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sdram_command(enum fmc_sdram_bank bank,
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enum fmc_sdram_command cmd, int autorefresh, int modereg) {
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uint32_t tmp_reg = 0;
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switch (bank) {
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case SDRAM_BANK1:
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tmp_reg = FMC_SDCMR_CTB1;
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break;
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case SDRAM_BANK2:
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tmp_reg = FMC_SDCMR_CTB2;
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break;
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case SDRAM_BOTH_BANKS:
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tmp_reg = FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2;
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break;
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}
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tmp_reg |= autorefresh << FMC_SDCMR_NRFS_SHIFT;
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tmp_reg |= modereg << FMC_SDCMR_MRD_SHIFT;
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switch (cmd) {
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case SDRAM_CLK_CONF:
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tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
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break;
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case SDRAM_AUTO_REFRESH:
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tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
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break;
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case SDRAM_LOAD_MODE:
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tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
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break;
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case SDRAM_PALL:
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tmp_reg |= FMC_SDCMR_MODE_PALL;
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break;
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case SDRAM_SELF_REFRESH:
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tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
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break;
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case SDRAM_POWER_DOWN:
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tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
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break;
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case SDRAM_NORMAL:
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default:
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break;
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}
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/* Wait for the next chance to talk to the controller */
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while (FMC_SDSR & FMC_SDSR_BUSY);
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/* Send the next command */
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FMC_SDCMR = tmp_reg;
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}
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