681 lines
20 KiB
C
681 lines
20 KiB
C
/** @defgroup can_defines CAN defines
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@ingroup STM32F_defines
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@brief <b>libopencm3 Defined Constants and Types for STM32 CAN </b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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@date 12 November 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CAN_H
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#define LIBOPENCM3_CAN_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/* --- Convenience macros -------------------------------------------------- */
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/* CAN register base addresses (for convenience) */
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/*****************************************************************************/
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/** @defgroup can_reg_base CAN register base address
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@ingroup can_defines
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@{*/
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#define CAN1 BX_CAN1_BASE
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#define CAN2 BX_CAN2_BASE
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/**@}*/
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/* --- CAN registers ------------------------------------------------------- */
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/* CAN master control register (CAN_MCR) */
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#define CAN_MCR(can_base) MMIO32((can_base) + 0x000)
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/* CAN master status register (CAN_MSR) */
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#define CAN_MSR(can_base) MMIO32((can_base) + 0x004)
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/* CAN transmit status register (CAN_TSR) */
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#define CAN_TSR(can_base) MMIO32((can_base) + 0x008)
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/* CAN receive FIFO 0 register (CAN_RF0R) */
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#define CAN_RF0R(can_base) MMIO32((can_base) + 0x00C)
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/* CAN receive FIFO 1 register (CAN_RF1R) */
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#define CAN_RF1R(can_base) MMIO32((can_base) + 0x010)
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/* CAN interrupt enable register (CAN_IER) */
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#define CAN_IER(can_base) MMIO32((can_base) + 0x014)
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/* CAN error status register (CAN_ESR) */
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#define CAN_ESR(can_base) MMIO32((can_base) + 0x018)
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/* CAN bit timing register (CAN_BTR) */
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#define CAN_BTR(can_base) MMIO32((can_base) + 0x01C)
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/* Registers in the offset range 0x020 to 0x17F are reserved. */
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/* --- CAN mailbox registers ----------------------------------------------- */
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/* CAN mailbox / FIFO register offsets */
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#define CAN_MBOX0 0x180
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#define CAN_MBOX1 0x190
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#define CAN_MBOX2 0x1A0
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#define CAN_FIFO0 0x1B0
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#define CAN_FIFO1 0x1C0
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/* CAN TX mailbox identifier register (CAN_TIxR) */
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#define CAN_TIxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x0)
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#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
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#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
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#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
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/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
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#define CAN_TDTxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x4)
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#define CAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0)
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#define CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1)
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#define CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2)
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/* CAN mailbox data low register (CAN_TDLxR) */
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#define CAN_TDLxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x8)
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#define CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0)
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#define CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1)
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#define CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2)
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/* CAN mailbox data high register (CAN_TDHxR) */
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#define CAN_TDHxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0xC)
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#define CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0)
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#define CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1)
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#define CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2)
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/* CAN RX FIFO identifier register (CAN_RIxR) */
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#define CAN_RIxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x0)
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#define CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0)
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#define CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1)
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/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
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#define CAN_RDTxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x4)
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#define CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0)
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#define CAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1)
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/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
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#define CAN_RDLxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x8)
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#define CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0)
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#define CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1)
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/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
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#define CAN_RDHxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0xC)
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#define CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0)
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#define CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1)
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/* --- CAN filter registers ------------------------------------------------ */
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/* CAN filter master register (CAN_FMR) */
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#define CAN_FMR(can_base) MMIO32((can_base) + 0x200)
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/* CAN filter mode register (CAN_FM1R) */
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#define CAN_FM1R(can_base) MMIO32((can_base) + 0x204)
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/* Register offset 0x208 is reserved. */
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/* CAN filter scale register (CAN_FS1R) */
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#define CAN_FS1R(can_base) MMIO32((can_base) + 0x20C)
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/* Register offset 0x210 is reserved. */
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/* CAN filter FIFO assignement register (CAN_FFA1R) */
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#define CAN_FFA1R(can_base) MMIO32((can_base) + 0x214)
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/* Register offset 0x218 is reserved. */
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/* CAN filter activation register (CAN_FA1R) */
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#define CAN_FA1R(can_base) MMIO32((can_base) + 0x21C)
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/* Register offset 0x220 is reserved. */
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/* Registers with offset 0x224 to 0x23F are reserved. */
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/* CAN filter bank registers (CAN_FiRx) */
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/*
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* Connectivity line devices have 28 banks so the bank ID spans 0..27
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* all other devices have 14 banks so the bank ID spans 0..13.
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*/
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#define CAN_FiR1(can_base, bank) MMIO32((can_base) + 0x240 + \
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((bank) * 0x8) + 0x0)
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#define CAN_FiR2(can_base, bank) MMIO32((can_base) + 0x240 + \
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((bank) * 0x8) + 0x4)
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/* --- CAN_MCR values ------------------------------------------------------ */
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/* 31:17 Reserved, forced by hardware to 0 */
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/* DBF: Debug freeze */
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#define CAN_MCR_DBF (1 << 16)
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/* RESET: bxCAN software master reset */
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#define CAN_MCR_RESET (1 << 15)
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/* 14:8 Reserved, forced by hardware to 0 */
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/* TTCM: Time triggered communication mode */
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#define CAN_MCR_TTCM (1 << 7)
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/* ABOM: Automatic bus-off management */
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#define CAN_MCR_ABOM (1 << 6)
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/* AWUM: Automatic wakeup mode */
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#define CAN_MCR_AWUM (1 << 5)
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/* NART: No automatic retransmission */
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#define CAN_MCR_NART (1 << 4)
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/* RFLM: Receive FIFO locked mode */
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#define CAN_MCR_RFLM (1 << 3)
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/* TXFP: Transmit FIFO priority */
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#define CAN_MCR_TXFP (1 << 2)
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/* SLEEP: Sleep mode request */
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#define CAN_MCR_SLEEP (1 << 1)
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/* INRQ: Initialization request */
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#define CAN_MCR_INRQ (1 << 0)
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/* --- CAN_MSR values ------------------------------------------------------ */
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/* 31:12 Reserved, forced by hardware to 0 */
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/* RX: CAN Rx signal */
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#define CAN_MSR_RX (1 << 11)
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/* SAMP: Last sample point */
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#define CAN_MSR_SAMP (1 << 10)
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/* RXM: Receive mode */
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#define CAN_MSR_RXM (1 << 9)
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/* TXM: Transmit mode */
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#define CAN_MSR_TXM (1 << 8)
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/* 7:5 Reserved, forced by hardware to 0 */
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/* SLAKI: Sleep acknowledge interrupt */
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#define CAN_MSR_SLAKI (1 << 4)
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/* WKUI: Wakeup interrupt */
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#define CAN_MSR_WKUI (1 << 3)
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/* ERRI: Error interrupt */
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#define CAN_MSR_ERRI (1 << 2)
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/* SLAK: Sleep acknowledge */
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#define CAN_MSR_SLAK (1 << 1)
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/* INAK: Initialization acknowledge */
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#define CAN_MSR_INAK (1 << 0)
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/* --- CAN_TSR values ------------------------------------------------------ */
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/* LOW2: Lowest priority flag for mailbox 2 */
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#define CAN_TSR_LOW2 (1 << 31)
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/* LOW1: Lowest priority flag for mailbox 1 */
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#define CAN_TSR_LOW1 (1 << 30)
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/* LOW0: Lowest priority flag for mailbox 0 */
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#define CAN_TSR_LOW0 (1 << 29)
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/* TME2: Transmit mailbox 2 empty */
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#define CAN_TSR_TME2 (1 << 28)
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/* TME1: Transmit mailbox 1 empty */
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#define CAN_TSR_TME1 (1 << 27)
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/* TME0: Transmit mailbox 0 empty */
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#define CAN_TSR_TME0 (1 << 26)
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/* CODE[1:0]: Mailbox code */
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#define CAN_TSR_CODE_MASK (0x3 << 24)
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/* ABRQ2: Abort request for mailbox 2 */
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#define CAN_TSR_ABRQ2 (1 << 23)
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/* 22:20 Reserved, forced by hardware to 0 */
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/* TERR2: Transmission error for mailbox 2 */
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#define CAN_TSR_TERR2 (1 << 19)
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/* ALST2: Arbitration lost for mailbox 2 */
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#define CAN_TSR_ALST2 (1 << 18)
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/* TXOK2: Transmission OK for mailbox 2 */
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#define CAN_TSR_TXOK2 (1 << 17)
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/* RQCP2: Request completed mailbox 2 */
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#define CAN_TSR_RQCP2 (1 << 16)
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/* ABRQ1: Abort request for mailbox 1 */
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#define CAN_TSR_ABRQ1 (1 << 15)
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/* 14:12 Reserved, forced by hardware to 0 */
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/* TERR1: Transmission error for mailbox 1 */
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#define CAN_TSR_TERR1 (1 << 11)
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/* ALST1: Arbitration lost for mailbox 1 */
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#define CAN_TSR_ALST1 (1 << 10)
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/* TXOK1: Transmission OK for mailbox 1 */
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#define CAN_TSR_TXOK1 (1 << 9)
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/* RQCP1: Request completed mailbox 1 */
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#define CAN_TSR_RQCP1 (1 << 8)
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/* ABRQ0: Abort request for mailbox 0 */
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#define CAN_TSR_ABRQ0 (1 << 7)
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/* 6:4 Reserved, forced by hardware to 0 */
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/* TERR0: Transmission error for mailbox 0 */
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#define CAN_TSR_TERR0 (1 << 3)
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/* ALST0: Arbitration lost for mailbox 0 */
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#define CAN_TSR_ALST0 (1 << 2)
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/* TXOK0: Transmission OK for mailbox 0 */
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#define CAN_TSR_TXOK0 (1 << 1)
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/* RQCP0: Request completed mailbox 0 */
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#define CAN_TSR_RQCP0 (1 << 0)
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/* --- CAN_RF0R values ----------------------------------------------------- */
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/* 31:6 Reserved, forced by hardware to 0 */
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/* RFOM0: Release FIFO 0 output mailbox */
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#define CAN_RF0R_RFOM0 (1 << 5)
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/* FOVR0: FIFO 0 overrun */
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#define CAN_RF0R_FOVR0 (1 << 4)
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/* FULL0: FIFO 0 full */
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#define CAN_RF0R_FULL0 (1 << 3)
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/* 2 Reserved, forced by hardware to 0 */
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/* FMP0[1:0]: FIFO 0 message pending */
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#define CAN_RF0R_FMP0_MASK (0x3 << 0)
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/* --- CAN_RF1R values ----------------------------------------------------- */
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/* 31:6 Reserved, forced by hardware to 0 */
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/* RFOM1: Release FIFO 1 output mailbox */
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#define CAN_RF1R_RFOM1 (1 << 5)
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/* FOVR1: FIFO 1 overrun */
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#define CAN_RF1R_FOVR1 (1 << 4)
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/* FULL1: FIFO 1 full */
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#define CAN_RF1R_FULL1 (1 << 3)
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/* 2 Reserved, forced by hardware to 0 */
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/* FMP1[1:0]: FIFO 1 message pending */
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#define CAN_RF1R_FMP1_MASK (0x3 << 0)
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/* --- CAN_IER values ------------------------------------------------------ */
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/* 32:18 Reserved, forced by hardware to 0 */
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/* SLKIE: Sleep interrupt enable */
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#define CAN_IER_SLKIE (1 << 17)
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/* WKUIE: Wakeup interrupt enable */
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#define CAN_IER_WKUIE (1 << 16)
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/* ERRIE: Error interrupt enable */
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#define CAN_IER_ERRIE (1 << 15)
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/* 14:12 Reserved, forced by hardware to 0 */
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/* LECIE: Last error code interrupt enable */
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#define CAN_IER_LECIE (1 << 11)
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/* BOFIE: Bus-off interrupt enable */
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#define CAN_IER_BOFIE (1 << 10)
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/* EPVIE: Error passive interrupt enable */
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#define CAN_IER_EPVIE (1 << 9)
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/* EWGIE: Error warning interrupt enable */
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#define CAN_IER_EWGIE (1 << 8)
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/* 7 Reserved, forced by hardware to 0 */
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/* FOVIE1: FIFO overrun interrupt enable */
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#define CAN_IER_FOVIE1 (1 << 6)
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/* FFIE1: FIFO full interrupt enable */
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#define CAN_IER_FFIE1 (1 << 5)
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/* FMPIE1: FIFO message pending interrupt enable */
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#define CAN_IER_FMPIE1 (1 << 4)
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/* FOVIE0: FIFO overrun interrupt enable */
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#define CAN_IER_FOVIE0 (1 << 3)
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/* FFIE0: FIFO full interrupt enable */
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#define CAN_IER_FFIE0 (1 << 2)
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/* FMPIE0: FIFO message pending interrupt enable */
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#define CAN_IER_FMPIE0 (1 << 1)
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/* TMEIE: Transmit mailbox empty interrupt enable */
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#define CAN_IER_TMEIE (1 << 0)
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/* --- CAN_ESR values ------------------------------------------------------ */
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/* REC[7:0]: Receive error counter */
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#define CAN_ESR_REC_MASK (0xF << 24)
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/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
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#define CAN_ESR_TEC_MASK (0xF << 16)
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/* 15:7 Reserved, forced by hardware to 0 */
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/* LEC[2:0]: Last error code */
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#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
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#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
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#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
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#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
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#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
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#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
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#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
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#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
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#define CAN_ESR_LEC_MASK (0x7 << 4)
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/* 3 Reserved, forced by hardware to 0 */
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/* BOFF: Bus-off flag */
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#define CAN_ESR_BOFF (1 << 2)
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/* EPVF: Error passive flag */
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#define CAN_ESR_EPVF (1 << 1)
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/* EWGF: Error warning flag */
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#define CAN_ESR_EWGF (1 << 0)
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/* --- CAN_BTR values ------------------------------------------------------ */
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/* SILM: Silent mode (debug) */
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#define CAN_BTR_SILM (1 << 31)
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/* LBKM: Loop back mode (debug) */
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#define CAN_BTR_LBKM (1 << 30)
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/* 29:26 Reserved, forced by hardware to 0 */
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/* SJW[1:0]: Resynchronization jump width */
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#define CAN_BTR_SJW_1TQ (0x0 << 24)
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#define CAN_BTR_SJW_2TQ (0x1 << 24)
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#define CAN_BTR_SJW_3TQ (0x2 << 24)
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#define CAN_BTR_SJW_4TQ (0x3 << 24)
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#define CAN_BTR_SJW_MASK (0x3 << 24)
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#define CAN_BTR_SJW_SHIFT 24
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/* 23 Reserved, forced by hardware to 0 */
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/* TS2[2:0]: Time segment 2 */
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#define CAN_BTR_TS2_1TQ (0x0 << 20)
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#define CAN_BTR_TS2_2TQ (0x1 << 20)
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#define CAN_BTR_TS2_3TQ (0x2 << 20)
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#define CAN_BTR_TS2_4TQ (0x3 << 20)
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#define CAN_BTR_TS2_5TQ (0x4 << 20)
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#define CAN_BTR_TS2_6TQ (0x5 << 20)
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#define CAN_BTR_TS2_7TQ (0x6 << 20)
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#define CAN_BTR_TS2_8TQ (0x7 << 20)
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#define CAN_BTR_TS2_MASK (0x7 << 20)
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#define CAN_BTR_TS2_SHIFT 20
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/* TS1[3:0]: Time segment 1 */
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#define CAN_BTR_TS1_1TQ (0x0 << 16)
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#define CAN_BTR_TS1_2TQ (0x1 << 16)
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#define CAN_BTR_TS1_3TQ (0x2 << 16)
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#define CAN_BTR_TS1_4TQ (0x3 << 16)
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#define CAN_BTR_TS1_5TQ (0x4 << 16)
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#define CAN_BTR_TS1_6TQ (0x5 << 16)
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#define CAN_BTR_TS1_7TQ (0x6 << 16)
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#define CAN_BTR_TS1_8TQ (0x7 << 16)
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#define CAN_BTR_TS1_9TQ (0x8 << 16)
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#define CAN_BTR_TS1_10TQ (0x9 << 16)
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#define CAN_BTR_TS1_11TQ (0xA << 16)
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#define CAN_BTR_TS1_12TQ (0xB << 16)
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#define CAN_BTR_TS1_13TQ (0xC << 16)
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#define CAN_BTR_TS1_14TQ (0xD << 16)
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#define CAN_BTR_TS1_15TQ (0xE << 16)
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#define CAN_BTR_TS1_16TQ (0xF << 16)
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#define CAN_BTR_TS1_MASK (0xF << 16)
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#define CAN_BTR_TS1_SHIFT 16
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/* 15:10 Reserved, forced by hardware to 0 */
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/* BRP[9:0]: Baud rate prescaler */
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#define CAN_BTR_BRP_MASK (0x3FFUL << 0)
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/* --- CAN_TIxR values ------------------------------------------------------ */
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/* STID[10:0]: Standard identifier */
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#define CAN_TIxR_STID_MASK (0x7FF << 21)
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#define CAN_TIxR_STID_SHIFT 21
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/* EXID[15:0]: Extended identifier */
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#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
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#define CAN_TIxR_EXID_SHIFT 3
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/* IDE: Identifier extension */
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#define CAN_TIxR_IDE (1 << 2)
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/* RTR: Remote transmission request */
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#define CAN_TIxR_RTR (1 << 1)
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/* TXRQ: Transmit mailbox request */
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#define CAN_TIxR_TXRQ (1 << 0)
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/* --- CAN_TDTxR values ----------------------------------------------------- */
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/* TIME[15:0]: Message time stamp */
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#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
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#define CAN_TDTxR_TIME_SHIFT 15
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/* 15:6 Reserved, forced by hardware to 0 */
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/* TGT: Transmit global time */
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#define CAN_TDTxR_TGT (1 << 5)
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/* 7:4 Reserved, forced by hardware to 0 */
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/* DLC[3:0]: Data length code */
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#define CAN_TDTxR_DLC_MASK (0xF << 0)
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#define CAN_TDTxR_DLC_SHIFT 0
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/* --- CAN_TDLxR values ----------------------------------------------------- */
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/* DATA3[7:0]: Data byte 3 */
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/* DATA2[7:0]: Data byte 2 */
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/* DATA1[7:0]: Data byte 1 */
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/* DATA0[7:0]: Data byte 0 */
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/* --- CAN_TDHxR values ----------------------------------------------------- */
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/* DATA7[7:0]: Data byte 7 */
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/* DATA6[7:0]: Data byte 6 */
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/* DATA5[7:0]: Data byte 5 */
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/* DATA4[7:0]: Data byte 4 */
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/* --- CAN_RIxR values ------------------------------------------------------ */
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/* STID[10:0]: Standard identifier */
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#define CAN_RIxR_STID_MASK (0x7FF)
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#define CAN_RIxR_STID_SHIFT 21
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/* EXID[15:0]: Extended identifier */
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#define CAN_RIxR_EXID_MASK (0x1FFFFFFF)
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#define CAN_RIxR_EXID_SHIFT 3
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/* IDE: Identifier extension */
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#define CAN_RIxR_IDE (1 << 2)
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/* RTR: Remote transmission request */
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#define CAN_RIxR_RTR (1 << 1)
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/* 0 Reserved */
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/* --- CAN_RDTxR values ----------------------------------------------------- */
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/* TIME[15:0]: Message time stamp */
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#define CAN_RDTxR_TIME_MASK (0xFFFF << 16)
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#define CAN_RDTxR_TIME_SHIFT 16
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/* FMI[7:0]: Filter match index */
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#define CAN_RDTxR_FMI_MASK (0xFF << 8)
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#define CAN_RDTxR_FMI_SHIFT 8
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/* 7:4 Reserved, forced by hardware to 0 */
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/* DLC[3:0]: Data length code */
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#define CAN_RDTxR_DLC_MASK (0xF << 0)
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#define CAN_RDTxR_DLC_SHIFT 0
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/* --- CAN_RDLxR values ----------------------------------------------------- */
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/* DATA3[7:0]: Data byte 3 */
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/* DATA2[7:0]: Data byte 2 */
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/* DATA1[7:0]: Data byte 1 */
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/* DATA0[7:0]: Data byte 0 */
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/* --- CAN_RDHxR values ----------------------------------------------------- */
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/* DATA7[7:0]: Data byte 7 */
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/* DATA6[7:0]: Data byte 6 */
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/* DATA5[7:0]: Data byte 5 */
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/* DATA4[7:0]: Data byte 4 */
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/* --- CAN_FMR values ------------------------------------------------------- */
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|
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/* 31:14 Reserved, forced to reset value */
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|
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/*
|
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* CAN2SB[5:0]: CAN2 start bank
|
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* (only on connectivity line devices otherwise reserved)
|
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*/
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#define CAN_FMR_CAN2SB_SHIFT 8
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#define CAN_FMR_CAN2SB_MASK (0x3F << CAN_FMR_CAN2SB_SHIFT)
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|
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/* 7:1 Reserved, forced to reset value */
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|
|
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/* FINIT: Filter init mode */
|
|
#define CAN_FMR_FINIT (1 << 0)
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|
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/* --- CAN_FM1R values ------------------------------------------------------ */
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|
|
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/* 31:28 Reserved, forced by hardware to 0 */
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|
|
|
/*
|
|
* FBMx: Filter mode
|
|
* x is 0..27 should be calculated by a helper function making so many macros
|
|
* seems like an overkill?
|
|
*/
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|
|
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/* --- CAN_FS1R values ------------------------------------------------------ */
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|
|
|
/* 31:28 Reserved, forced by hardware to 0 */
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|
|
|
/*
|
|
* FSCx: Filter scale configuration
|
|
* x is 0..27 should be calculated by a helper function making so many macros
|
|
* seems like an overkill?
|
|
*/
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|
|
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/* --- CAN_FFA1R values ----------------------------------------------------- */
|
|
|
|
/* 31:28 Reserved, forced by hardware to 0 */
|
|
|
|
/*
|
|
* FFAx: Filter scale configuration
|
|
* x is 0..27 should be calculated by a helper function making so many macros
|
|
* seems like an overkill?
|
|
*/
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|
|
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/* --- CAN_FA1R values ------------------------------------------------------ */
|
|
|
|
/* 31:28 Reserved, forced by hardware to 0 */
|
|
|
|
/*
|
|
* FACTx: Filter active
|
|
* x is 0..27 should be calculated by a helper function making so many macros
|
|
* seems like an overkill?
|
|
*/
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|
|
|
/* --- CAN_FiRx values ------------------------------------------------------ */
|
|
|
|
/* FB[31:0]: Filter bits */
|
|
|
|
/* --- CAN functions -------------------------------------------------------- */
|
|
|
|
BEGIN_DECLS
|
|
|
|
void can_reset(uint32_t canport);
|
|
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
|
|
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
|
|
uint32_t brp, bool loopback, bool silent);
|
|
|
|
void can_filter_init(uint32_t nr, bool scale_32bit,
|
|
bool id_list_mode, uint32_t fr1, uint32_t fr2,
|
|
uint32_t fifo, bool enable);
|
|
void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1,
|
|
uint16_t mask1, uint16_t id2,
|
|
uint16_t mask2, uint32_t fifo, bool enable);
|
|
void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id,
|
|
uint32_t mask, uint32_t fifo, bool enable);
|
|
void can_filter_id_list_16bit_init(uint32_t nr, uint16_t id1,
|
|
uint16_t id2, uint16_t id3, uint16_t id4,
|
|
uint32_t fifo, bool enable);
|
|
void can_filter_id_list_32bit_init(uint32_t nr, uint32_t id1,
|
|
uint32_t id2, uint32_t fifo, bool enable);
|
|
|
|
void can_enable_irq(uint32_t canport, uint32_t irq);
|
|
void can_disable_irq(uint32_t canport, uint32_t irq);
|
|
|
|
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
|
|
uint8_t length, uint8_t *data);
|
|
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
|
|
bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length,
|
|
uint8_t *data, uint16_t *timestamp);
|
|
|
|
void can_fifo_release(uint32_t canport, uint8_t fifo);
|
|
bool can_available_mailbox(uint32_t canport);
|
|
END_DECLS
|
|
|
|
/**@}*/
|
|
#endif
|