634 lines
14 KiB
C
634 lines
14 KiB
C
/** @defgroup STM32F0xx-rcc-file RCC
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*
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* @ingroup STM32F0xx
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*
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* @brief <b>libopencm3 STM32F0xx Reset and Clock Control</b>
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*
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* @version 1.0.0
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*
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* @date 29 Jun 2013
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*
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* This library supports the Reset and Clock Control System in the STM32F0xx
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* series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/flash.h>
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/* Set the default clock frequencies */
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uint32_t rcc_ahb_frequency = 8000000; /* 8MHz after reset */
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uint32_t rcc_apb1_frequency = 8000000; /* 8MHz after reset */
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Oscillator Ready Interrupt Flag
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*
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* Clear the interrupt flag that was set when a clock oscillator became ready
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* to use.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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RCC_CIR |= RCC_CIR_HSI48RDYC;
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break;
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case HSI14:
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RCC_CIR |= RCC_CIR_HSI14RDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable the Oscillator Ready Interrupt
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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RCC_CIR |= RCC_CIR_HSI48RDYIE;
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break;
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case HSI14:
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RCC_CIR |= RCC_CIR_HSI14RDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable the Oscillator Ready Interrupt
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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RCC_CIR &= ~RCC_CIR_HSI48RDYC;
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break;
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case HSI14:
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RCC_CIR &= ~RCC_CIR_HSI14RDYC;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYC;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYC;
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break;
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYC;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYC;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Read the Oscillator Ready Interrupt Flag
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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* @returns int. Boolean value for flag set.
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*/
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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return (RCC_CIR & RCC_CIR_HSI48RDYF) != 0;
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break;
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case HSI14:
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return (RCC_CIR & RCC_CIR_HSI14RDYF) != 0;
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break;
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case HSI:
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return (RCC_CIR & RCC_CIR_HSIRDYF) != 0;
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break;
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case HSE:
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return (RCC_CIR & RCC_CIR_HSERDYF) != 0;
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break;
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case PLL:
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return (RCC_CIR & RCC_CIR_PLLRDYF) != 0;
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break;
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case LSE:
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return (RCC_CIR & RCC_CIR_LSERDYF) != 0;
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break;
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case LSI:
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return (RCC_CIR & RCC_CIR_LSIRDYF) != 0;
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break;
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}
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cm3_assert_not_reached();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Clock Security System Interrupt Flag
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*/
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Read the Clock Security System Interrupt Flag
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*
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* @returns int. Boolean value for flag set.
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*/
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Wait for Oscillator Ready.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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while ((RCC_CIR & RCC_CIR_HSI48RDYF) != 0);
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break;
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case HSI14:
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while ((RCC_CIR & RCC_CIR_HSI14RDYF) != 0);
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break;
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case HSI:
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while ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case HSE:
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while ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case PLL:
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while ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case LSE:
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while ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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while ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Turn on an Oscillator.
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*
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* Enable an oscillator and power on. Each oscillator requires an amount of
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* time to settle to a usable state. Refer to datasheets for time delay
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* information. A status flag is available to indicate when the oscillator
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* becomes ready (see @ref rcc_osc_ready_int_flag and @ref
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* rcc_wait_for_osc_ready).
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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RCC_CR2 |= RCC_CR2_HSI48ON;
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break;
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case HSI14:
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RCC_CR2 |= RCC_CR2_HSI14ON;
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break;
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case HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Turn off an Oscillator.
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*
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* Disable an oscillator and power off.
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*
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* @note An oscillator cannot be turned off if it is selected as the system
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* clock.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case HSI48:
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RCC_CR2 &= ~RCC_CR2_HSI48ON;
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break;
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case HSI14:
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RCC_CR2 &= ~RCC_CR2_HSI14ON;
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break;
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case HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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case PLL:
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/* don't do anything */
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable the Clock Security System.
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*/
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable the Clock Security System.
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*/
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable Bypass.
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*
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* Enable an external clock to bypass the internal clock (high speed and low
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* speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
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* and the internal clock must be disabled (see @ref rcc_osc_off) for this to
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* have effect.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
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*/
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void rcc_osc_bypass_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case HSI48:
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case HSI14:
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case HSI:
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case LSI:
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case PLL:
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/* Do nothing */
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable Bypass.
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*
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* Re-enable the internal clock (high speed and low speed clocks only). The
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* internal clock must be disabled (see @ref rcc_osc_off) for this to have
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* effect.
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*
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*
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* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
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*/
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void rcc_osc_bypass_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case HSI48:
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case HSI14:
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing */
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the Source for the System Clock.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, LSE and PLL have
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* effect.
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*/
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void rcc_set_sysclk_source(enum rcc_osc clk)
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{
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switch (clk) {
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case HSI:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSI;
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break;
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case HSE:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSE;
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break;
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case PLL:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
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break;
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case HSI48:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSI48;
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break;
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case LSI:
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case LSE:
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case HSI14:
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/* do nothing */
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Multiplication Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll_multiplication_factor(uint32_t mul)
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{
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RCC_CFGR = (RCC_CFGR & RCC_CFGR_PLLMUL) | mul;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB Prescale Factor.
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*
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* @note The APB1 clock frequency must not exceed 36MHz.
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*
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* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
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*/
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void rcc_set_ppre(uint32_t ppre)
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{
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE) | ppre;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the AHB Prescale Factor.
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*
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* @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
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*/
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void rcc_set_hpre(uint32_t hpre)
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{
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_HPRE) | hpre;
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}
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void rcc_set_prediv(uint32_t prediv)
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{
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RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv;
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}
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void rcc_set_mco(uint32_t mcosrc)
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{
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_MCO) | mcosrc;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Get the System Clock Source.
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*
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* @returns ::osc_t System clock source:
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*/
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enum rcc_osc rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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switch (RCC_CFGR & RCC_CFGR_SWS) {
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case RCC_CFGR_SWS_HSI:
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return HSI;
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case RCC_CFGR_SWS_HSE:
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return HSE;
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case RCC_CFGR_SWS_PLL:
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return PLL;
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case RCC_CFGR_SWS_HSI48:
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return HSI48;
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}
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cm3_assert_not_reached();
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}
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void rcc_clock_setup_in_hsi_out_8mhz(void)
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{
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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rcc_set_sysclk_source(HSI);
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
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rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
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flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ);
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rcc_apb1_frequency = 8000000;
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rcc_ahb_frequency = 8000000;
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}
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void rcc_clock_setup_in_hsi_out_16mhz(void)
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{
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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rcc_set_sysclk_source(HSI);
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
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rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
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flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ);
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/* 8MHz * 4 / 2 = 16MHz */
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4);
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RCC_CFGR &= ~RCC_CFGR_PLLSRC;
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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rcc_set_sysclk_source(PLL);
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rcc_apb1_frequency = 16000000;
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rcc_ahb_frequency = 16000000;
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}
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void rcc_clock_setup_in_hsi_out_24mhz(void)
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{
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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rcc_set_sysclk_source(HSI);
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
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rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
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flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ);
|
|
|
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/* 8MHz * 6 / 2 = 24MHz */
|
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6);
|
|
|
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RCC_CFGR &= ~RCC_CFGR_PLLSRC;
|
|
|
|
rcc_osc_on(PLL);
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|
rcc_wait_for_osc_ready(PLL);
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|
rcc_set_sysclk_source(PLL);
|
|
|
|
rcc_apb1_frequency = 24000000;
|
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rcc_ahb_frequency = 24000000;
|
|
}
|
|
|
|
void rcc_clock_setup_in_hsi_out_32mhz(void)
|
|
{
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|
rcc_osc_on(HSI);
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|
rcc_wait_for_osc_ready(HSI);
|
|
rcc_set_sysclk_source(HSI);
|
|
|
|
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
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rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
|
|
|
|
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
|
|
|
|
/* 8MHz * 8 / 2 = 32MHz */
|
|
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL8);
|
|
|
|
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
|
|
|
|
rcc_osc_on(PLL);
|
|
rcc_wait_for_osc_ready(PLL);
|
|
rcc_set_sysclk_source(PLL);
|
|
|
|
rcc_apb1_frequency = 32000000;
|
|
rcc_ahb_frequency = 32000000;
|
|
}
|
|
|
|
void rcc_clock_setup_in_hsi_out_40mhz(void)
|
|
{
|
|
rcc_osc_on(HSI);
|
|
rcc_wait_for_osc_ready(HSI);
|
|
rcc_set_sysclk_source(HSI);
|
|
|
|
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
|
|
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
|
|
|
|
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
|
|
|
|
/* 8MHz * 10 / 2 = 40MHz */
|
|
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10);
|
|
|
|
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
|
|
|
|
rcc_osc_on(PLL);
|
|
rcc_wait_for_osc_ready(PLL);
|
|
rcc_set_sysclk_source(PLL);
|
|
|
|
rcc_apb1_frequency = 40000000;
|
|
rcc_ahb_frequency = 40000000;
|
|
}
|
|
|
|
void rcc_clock_setup_in_hsi_out_48mhz(void)
|
|
{
|
|
rcc_osc_on(HSI);
|
|
rcc_wait_for_osc_ready(HSI);
|
|
rcc_set_sysclk_source(HSI);
|
|
|
|
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
|
|
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
|
|
|
|
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
|
|
|
|
/* 8MHz * 12 / 2 = 48MHz */
|
|
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
|
|
|
|
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
|
|
|
|
rcc_osc_on(PLL);
|
|
rcc_wait_for_osc_ready(PLL);
|
|
rcc_set_sysclk_source(PLL);
|
|
|
|
rcc_apb1_frequency = 48000000;
|
|
rcc_ahb_frequency = 48000000;
|
|
}
|
|
|
|
/**@}*/
|
|
|