142 lines
4.5 KiB
C
142 lines
4.5 KiB
C
/**
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* @brief Clock Control and System Defines for the Qorvo PAC55xx series of microcontrollers.
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*
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* @defgroup system_defines Clock Config and System Defines
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* @ingroup PAC55xx_defines
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* @author Brian Viele <vielster@allocor.tech>
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* LGPL License Terms @ref lgpl_license
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* @date 1 Dec 2019
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*
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* Definitions in this file come from the PAC55XX Family User Guide Rev 1.21
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* by Active-Semi dated August 26, 2019.
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_
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#define INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/** Clock Control Registers
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* @defgroup clock_config_regs Clock Config Registers.
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* @{*/
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#define CCSCTL MMIO32(SCC_BASE)
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#define CCSPLLCTL MMIO32(SCC_BASE + 0x04)
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#define CCSROSCTRIM MMIO32(SCC_BASE + 0x08)
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/**@}*/
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/** Port Pin Config Addresses
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* @defgroup port_pin_addresses Port Pinmux Register Base.
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* @{*/
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#define CCS_PORTA (SCC_BASE + 0x0C)
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#define CCS_PORTB (SCC_BASE + 0x10)
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#define CCS_PORTC (SCC_BASE + 0x14)
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#define CCS_PORTD (SCC_BASE + 0x18)
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#define CCS_PORTE (SCC_BASE + 0x1C)
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#define CCS_PORTF (SCC_BASE + 0x20)
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#define CCS_PORTG (SCC_BASE + 0x24)
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/**@}*/
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/** Port Pin Mux Select Registers
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* @defgroup pmux_sel_regs PMUXSEL register mapping.
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* @{*/
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#define CCS_MUXSELR(base) MMIO32(base)
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#define CCS_PAMUXSELR CCS_MUXSELR(CCS_PORTA)
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#define CCS_PBMUXSELR CCS_MUXSELR(CCS_PORTB)
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#define CCS_PCMUXSELR CCS_MUXSELR(CCS_PORTC)
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#define CCS_PDMUXSELR CCS_MUXSELR(CCS_PORTD)
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#define CCS_PEMUXSELR CCS_MUXSELR(CCS_PORTE)
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#define CCS_PFMUXSELR CCS_MUXSELR(CCS_PORTF)
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#define CCS_PGMUXSELR CCS_MUXSELR(CCS_PORTG)
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#define CCS_MUXSELR_MASK 0x7
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#define CCS_MUXSELR_MASK_PIN(pin) (CCS_MUXSELR_MASK << ((pin) * 4))
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#define CCS_MUXSELR_VAL(pin, muxsel) (((muxsel) & CCS_MUXSELR_MASK) << ((pin) * 4))
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/* Enum type for port function setting for type specificity. */
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typedef enum {
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CCS_MUXSEL_GPIO = 0,
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CCS_MUXSEL_AF1 = 1,
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CCS_MUXSEL_AF2 = 2,
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CCS_MUXSEL_AF3 = 3,
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CCS_MUXSEL_AF4 = 4,
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CCS_MUXSEL_AF5 = 5,
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CCS_MUXSEL_AF6 = 6,
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CCS_MUXSEL_AF7 = 7,
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} ccs_muxsel_func_t;
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/**@}*/
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/** Port Pull-Up/Down Enable Registers.
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* @defgroup pden_regs PUEN PDEN register mapping.
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* @{*/
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#define CCS_PUENR(base) MMIO32(base + 0x1C)
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#define CCS_PAPUENR CCS_PUENR(CCS_PORTA)
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#define CCS_PBPUENR CCS_PUENR(CCS_PORTB)
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#define CCS_PCPUENR CCS_PUENR(CCS_PORTC)
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#define CCS_PDPUENR CCS_PUENR(CCS_PORTD)
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#define CCS_PEPUENR CCS_PUENR(CCS_PORTE)
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#define CCS_PFPUENR CCS_PUENR(CCS_PORTF)
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#define CCS_PGPUENR CCS_PUENR(CCS_PORTG)
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#define CCS_PDENR(base) MMIO32(base + 0x38)
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#define CCS_PAPDENR CCS_PDENR(CCS_PORTA)
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#define CCS_PBPDENR CCS_PDENR(CCS_PORTB)
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#define CCS_PCPDENR CCS_PDENR(CCS_PORTC)
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#define CCS_PDPDENR CCS_PDENR(CCS_PORTD)
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#define CCS_PEPDENR CCS_PDENR(CCS_PORTE)
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#define CCS_PFPDENR CCS_PDENR(CCS_PORTF)
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#define CCS_PGPDENR CCS_PDENR(CCS_PORTG)
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/** Pull Up/Down enum for type specificity. */
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typedef enum {
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CCS_IO_PULL_NONE = 0,
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CCS_IO_PULL_UP = 1,
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CCS_IO_PULL_DOWN = 2
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} ccs_pull_updown_t;
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/**@}*/
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/** Port Drive Strength Enable Registers.
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* @defgroup dsr_regs DSR register mapping.
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* @{*/
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#define CCS_DSR(base) MMIO32(base + 0x54)
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#define CCS_PADSR CCS_DSR(CCS_PORTA)
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#define CCS_PBDSR CCS_DSR(CCS_PORTB)
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#define CCS_PCDSR CCS_DSR(CCS_PORTC)
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#define CCS_PDDSR CCS_DSR(CCS_PORTD)
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#define CCS_PEDSR CCS_DSR(CCS_PORTE)
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#define CCS_PFDSR CCS_DSR(CCS_PORTF)
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#define CCS_PGDSR CCS_DSR(CCS_PORTG)
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#define CCS_DSR_MASK 0x7
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#define CCS_DSR_MASK_PIN(pin) (CCS_DSR_MASK << ((pin) * 4))
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#define CCS_DSR_DS_VAL(pin, ds) (((ds)&CCS_DSR_MASK) << ((pin)*4))
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#define CCS_DSR_SCHMIDT_PIN(pin) (BIT0 << (((pin)*4) + 3))
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/** Drive strength enumeration for type specificity. */
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typedef enum {
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CCS_DSR_DS_6MA = 0x00,
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CCS_DSR_DS_8MA = 0x01,
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CCS_DSR_DS_11MA = 0x02,
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CCS_DSR_DS_14MA = 0x03,
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CCS_DSR_DS_17MA = 0x04,
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CCS_DSR_DS_20MA = 0x05,
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CCS_DSR_DS_22MA = 0x06,
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CCS_DSR_DS_25MA = 0x07,
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} ccs_drive_strength_t;
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/**@}*/
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/**@}*/
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#endif /* INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_ */
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