184 lines
6.1 KiB
C
184 lines
6.1 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_GPIO_H
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#define LIBOPENSTM32_GPIO_H
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#include <libopenstm32.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPIO port base addresses (for convenience) */
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#define GPIOA GPIO_PORT_A_BASE
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#define GPIOB GPIO_PORT_B_BASE
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#define GPIOC GPIO_PORT_C_BASE
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#define GPIOD GPIO_PORT_D_BASE
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#define GPIOE GPIO_PORT_E_BASE
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#define GPIOF GPIO_PORT_F_BASE
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#define GPIOG GPIO_PORT_G_BASE
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/* GPIO number definitions (for convenience) */
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/* GPIO pins with alternate functions */
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#define GPIO_USART_TX GPIO10
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#define GPIO_USART_RX GPIO11
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/* TODO */
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/* --- GPIO registers ------------------------------------------------------ */
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/* Port configuration register low (GPIOx_CRL) */
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#define GPIO_CRL(port) MMIO32(port + 0x00)
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#define GPIOA_CRL GPIO_CRL(GPIOA)
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#define GPIOB_CRL GPIO_CRL(GPIOB)
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#define GPIOC_CRL GPIO_CRL(GPIOC)
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#define GPIOD_CRL GPIO_CRL(GPIOD)
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#define GPIOE_CRL GPIO_CRL(GPIOE)
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#define GPIOF_CRL GPIO_CRL(GPIOF)
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#define GPIOG_CRL GPIO_CRL(GPIOG)
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/* Port configuration register low (GPIOx_CRH) */
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#define GPIO_CRH(port) MMIO32(port + 0x04)
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#define GPIOA_CRH GPIO_CRH(GPIOA)
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#define GPIOB_CRH GPIO_CRH(GPIOB)
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#define GPIOC_CRH GPIO_CRH(GPIOC)
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#define GPIOD_CRH GPIO_CRH(GPIOD)
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#define GPIOE_CRH GPIO_CRH(GPIOE)
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#define GPIOF_CRH GPIO_CRH(GPIOF)
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#define GPIOG_CRH GPIO_CRH(GPIOG)
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/* Port input data register (GPIOx_IDR) */
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#define GPIO_IDR(port) MMIO32(port + 0x08)
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#define GPIOA_IDR GPIO_IDR(GPIOA)
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#define GPIOB_IDR GPIO_IDR(GPIOB)
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#define GPIOC_IDR GPIO_IDR(GPIOC)
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#define GPIOD_IDR GPIO_IDR(GPIOD)
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#define GPIOE_IDR GPIO_IDR(GPIOE)
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#define GPIOF_IDR GPIO_IDR(GPIOF)
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#define GPIOG_IDR GPIO_IDR(GPIOG)
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/* Port output data register (GPIOx_ODR) */
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#define GPIO_ODR(port) MMIO32(port + 0x0c)
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#define GPIOA_ODR GPIO_ODR(GPIOA)
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#define GPIOB_ODR GPIO_ODR(GPIOB)
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#define GPIOC_ODR GPIO_ODR(GPIOC)
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#define GPIOD_ODR GPIO_ODR(GPIOD)
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#define GPIOE_ODR GPIO_ODR(GPIOE)
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#define GPIOF_ODR GPIO_ODR(GPIOF)
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#define GPIOG_ODR GPIO_ODR(GPIOG)
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/* Port bit set/reset register (GPIOx_BSRR) */
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#define GPIO_BSRR(port) MMIO32(port + 0x10)
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#define GPIOA_BSRR GPIO_BSRR(GPIOA)
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#define GPIOB_BSRR GPIO_BSRR(GPIOB)
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#define GPIOC_BSRR GPIO_BSRR(GPIOC)
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#define GPIOD_BSRR GPIO_BSRR(GPIOD)
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#define GPIOE_BSRR GPIO_BSRR(GPIOE)
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#define GPIOF_BSRR GPIO_BSRR(GPIOF)
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#define GPIOG_BSRR GPIO_BSRR(GPIOG)
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/* Port bit reset register (GPIOx_BRR) */
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#define GPIO_BRR(port) MMIO16(port + 0x14)
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#define GPIOA_BRR GPIO_BRR(GPIOA)
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#define GPIOB_BRR GPIO_BRR(GPIOB)
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#define GPIOC_BRR GPIO_BRR(GPIOC)
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#define GPIOD_BRR GPIO_BRR(GPIOD)
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#define GPIOE_BRR GPIO_BRR(GPIOE)
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#define GPIOF_BRR GPIO_BRR(GPIOF)
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#define GPIOG_BRR GPIO_BRR(GPIOG)
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/* Port configuration lock register (GPIOx_LCKR) */
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#define GPIO_LCKR(port) MMIO32(port + 0x18)
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#define GPIOA_LCKR GPIO_LCKR(GPIOA)
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#define GPIOB_LCKR GPIO_LCKR(GPIOB)
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#define GPIOC_LCKR GPIO_LCKR(GPIOC)
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#define GPIOD_LCKR GPIO_LCKR(GPIOD)
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#define GPIOE_LCKR GPIO_LCKR(GPIOE)
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#define GPIOF_LCKR GPIO_LCKR(GPIOF)
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#define GPIOG_LCKR GPIO_LCKR(GPIOG)
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/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
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/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
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#define GPIO_CNF_INPUT_ANALOG 0x00
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#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
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#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
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/* Output mode (MODE[1:0]) values */
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#define GPIO_MODE_INPUT 0x00 /* Default */
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#define GPIO_MODE_OUTPUT_10_MHZ 0x01
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#define GPIO_MODE_OUTPUT_2_MHZ 0x02
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#define GPIO_MODE_OUTPUT_50_MHZ 0x03
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/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
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#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
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#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
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#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
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#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
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/* --- GPIO_IDR values ----------------------------------------------------- */
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/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
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/* --- GPIO_ODR values ----------------------------------------------------- */
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/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
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/* --- GPIO_BSRR values ---------------------------------------------------- */
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/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
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/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
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/* --- GPIO_BRR values ----------------------------------------------------- */
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/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
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/* --- GPIO_LCKR values ---------------------------------------------------- */
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#define GPIO_LCKK (1 << 16)
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/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
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/* --- Function prototypes ------------------------------------------------- */
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void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
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void gpio_set(u32 gpioport, u16 gpios);
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void gpio_clear(u32 gpioport, u16 gpios);
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u16 gpio_get(u32 gpioport, u16 gpios);
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void gpio_toggle(u32 gpioport, u16 gpios);
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u16 gpio_port_read(u32 gpioport);
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void gpio_port_write(u32 gpioport, u16 data);
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#endif
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