120 lines
5.0 KiB
C
120 lines
5.0 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- STM32 specific peripheral definitions ------------------------------- */
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/* Memory map for all busses */
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#define FLASH_BASE ((u32)0x08000000)
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#define PERIPH_BASE ((u32)0x40000000)
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#define INFO_BASE ((u32)0x1ffff000)
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
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#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
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#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
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#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
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#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
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#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
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#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
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/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
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#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
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#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
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/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
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#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
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#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
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#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
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#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
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/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */
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#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
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/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
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/* APB2 */
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#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
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#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400)
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#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00)
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#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000)
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
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#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800)
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)
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/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */
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#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00)
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#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000)
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#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400)
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/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */
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/* AHB */
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#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000)
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/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */
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#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000)
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#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400)
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/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */
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#define RCC_BASE (PERIPH_BASE_AHB + 0x09000)
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/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)
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#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000)
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/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */
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#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
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/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */
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#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000)
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/* PPIB */
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#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
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/* FSMC */
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#define FSMC_BASE (PERIPH_BASE + 0x60000000)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
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#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)
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#endif
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