887 lines
35 KiB
C
887 lines
35 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* Timer register base adresses (for convenience) */
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#define TIM1 TIM1_BASE
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#define TIM2 TIM2_BASE
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#define TIM3 TIM3_BASE
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#define TIM4 TIM4_BASE
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#define TIM5 TIM5_BASE
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#define TIM6 TIM6_BASE
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#define TIM7 TIM7_BASE
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#define TIM8 TIM8_BASE
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/* --- Timer registers ----------------------------------------------------- */
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/* Control register 1 (TIMx_CR1) */
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#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00)
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#define TIM1_CR1 TIM_CR1(TIM1)
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#define TIM2_CR1 TIM_CR1(TIM2)
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#define TIM3_CR1 TIM_CR1(TIM3)
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#define TIM4_CR1 TIM_CR1(TIM4)
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#define TIM5_CR1 TIM_CR1(TIM5)
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#define TIM6_CR1 TIM_CR1(TIM6)
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#define TIM7_CR1 TIM_CR1(TIM7)
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#define TIM8_CR1 TIM_CR1(TIM8)
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/* Control register 2 (TIMx_CR2) */
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#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04)
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#define TIM1_CR2 TIM_CR2(TIM1)
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#define TIM2_CR2 TIM_CR2(TIM2)
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#define TIM3_CR2 TIM_CR2(TIM3)
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#define TIM4_CR2 TIM_CR2(TIM4)
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#define TIM5_CR2 TIM_CR2(TIM5)
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#define TIM6_CR2 TIM_CR2(TIM6)
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#define TIM7_CR2 TIM_CR2(TIM7)
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#define TIM8_CR2 TIM_CR2(TIM8)
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/* Slave mode control register (TIMx_SMCR) */
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#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08)
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#define TIM1_SMCR TIM_SMCR(TIM1)
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#define TIM2_SMCR TIM_SMCR(TIM2)
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#define TIM3_SMCR TIM_SMCR(TIM3)
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#define TIM4_SMCR TIM_SMCR(TIM4)
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#define TIM5_SMCR TIM_SMCR(TIM5)
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#define TIM8_SMCR TIM_SMCR(TIM8)
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/* DMA/Interrupt enable register (TIMx_DIER) */
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#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C)
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#define TIM1_DIER TIM_DIER(TIM1)
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#define TIM2_DIER TIM_DIER(TIM2)
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#define TIM3_DIER TIM_DIER(TIM3)
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#define TIM4_DIER TIM_DIER(TIM4)
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#define TIM5_DIER TIM_DIER(TIM5)
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#define TIM6_DIER TIM_DIER(TIM6)
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#define TIM7_DIER TIM_DIER(TIM7)
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#define TIM8_DIER TIM_DIER(TIM8)
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/* Status register (TIMx_SR) */
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#define TIM_SR(tim_base) MMIO32(tim_base + 0x10)
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#define TIM1_SR TIM_SR(TIM1)
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#define TIM2_SR TIM_SR(TIM2)
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#define TIM3_SR TIM_SR(TIM3)
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#define TIM4_SR TIM_SR(TIM4)
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#define TIM5_SR TIM_SR(TIM5)
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#define TIM6_SR TIM_SR(TIM6)
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#define TIM7_SR TIM_SR(TIM7)
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#define TIM8_SR TIM_SR(TIM8)
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/* Event generation register (TIMx_EGR) */
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#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14)
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#define TIM1_EGR TIM_EGR(TIM1)
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#define TIM2_EGR TIM_EGR(TIM2)
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#define TIM3_EGR TIM_EGR(TIM3)
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#define TIM4_EGR TIM_EGR(TIM4)
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#define TIM5_EGR TIM_EGR(TIM5)
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#define TIM6_EGR TIM_EGR(TIM6)
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#define TIM7_EGR TIM_EGR(TIM7)
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#define TIM8_EGR TIM_EGR(TIM8)
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/* Capture/compare mode register 1 (TIMx_CCMR1) */
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#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18)
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#define TIM1_CCMR1 TIM_CCMR1(TIM1)
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#define TIM2_CCMR1 TIM_CCMR1(TIM2)
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#define TIM3_CCMR1 TIM_CCMR1(TIM3)
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#define TIM4_CCMR1 TIM_CCMR1(TIM4)
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#define TIM5_CCMR1 TIM_CCMR1(TIM5)
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#define TIM8_CCMR1 TIM_CCMR1(TIM8)
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/* Capture/compare mode register 2 (TIMx_CCMR2) */
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#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C)
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#define TIM1_CCMR2 TIM_CCMR2(TIM1)
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#define TIM2_CCMR2 TIM_CCMR2(TIM2)
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#define TIM3_CCMR2 TIM_CCMR2(TIM3)
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#define TIM4_CCMR2 TIM_CCMR2(TIM4)
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#define TIM5_CCMR2 TIM_CCMR2(TIM5)
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#define TIM8_CCMR2 TIM_CCMR2(TIM8)
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/* Capture/compare enable register (TIMx_CCER) */
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#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20)
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#define TIM1_CCER TIM_CCER(TIM1)
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#define TIM2_CCER TIM_CCER(TIM2)
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#define TIM3_CCER TIM_CCER(TIM3)
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#define TIM4_CCER TIM_CCER(TIM4)
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#define TIM5_CCER TIM_CCER(TIM5)
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#define TIM8_CCER TIM_CCER(TIM8)
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/* Counter (TIMx_CNT) */
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#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24)
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#define TIM1_CNT TIM_CNT(TIM1)
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#define TIM2_CNT TIM_CNT(TIM2)
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#define TIM3_CNT TIM_CNT(TIM3)
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#define TIM4_CNT TIM_CNT(TIM4)
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#define TIM5_CNT TIM_CNT(TIM5)
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#define TIM6_CNT TIM_CNT(TIM6)
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#define TIM7_CNT TIM_CNT(TIM7)
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#define TIM8_CNT TIM_CNT(TIM8)
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/* Prescaler (TIMx_PSC) */
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#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28)
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#define TIM1_PSC TIM_PSC(TIM1)
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#define TIM2_PSC TIM_PSC(TIM2)
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#define TIM3_PSC TIM_PSC(TIM3)
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#define TIM4_PSC TIM_PSC(TIM4)
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#define TIM5_PSC TIM_PSC(TIM5)
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#define TIM6_PSC TIM_PSC(TIM6)
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#define TIM7_PSC TIM_PSC(TIM7)
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#define TIM8_PSC TIM_PSC(TIM8)
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/* Auto-reload register (TIMx_ARR) */
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#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C)
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#define TIM1_ARR TIM_ARR(TIM1)
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#define TIM2_ARR TIM_ARR(TIM2)
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#define TIM3_ARR TIM_ARR(TIM3)
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#define TIM4_ARR TIM_ARR(TIM4)
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#define TIM5_ARR TIM_ARR(TIM5)
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#define TIM6_ARR TIM_ARR(TIM6)
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#define TIM7_ARR TIM_ARR(TIM7)
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#define TIM8_ARR TIM_ARR(TIM8)
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/* Repetition counter register (TIMx_RCR) */
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#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30)
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#define TIM1_RCR TIM_RCR(TIM1)
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#define TIM8_RCR TIM_RCR(TIM8)
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/* Capture/compare register 1 (TIMx_CCR1) */
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#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34)
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#define TIM1_CCR1 TIM_CCR1(TIM1)
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#define TIM2_CCR1 TIM_CCR1(TIM2)
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#define TIM3_CCR1 TIM_CCR1(TIM3)
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#define TIM4_CCR1 TIM_CCR1(TIM4)
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#define TIM5_CCR1 TIM_CCR1(TIM5)
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#define TIM8_CCR1 TIM_CCR1(TIM8)
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/* Capture/compare register 2 (TIMx_CCR2) */
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#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38)
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#define TIM1_CCR2 TIM_CCR2(TIM1)
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#define TIM2_CCR2 TIM_CCR2(TIM2)
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#define TIM3_CCR2 TIM_CCR2(TIM3)
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#define TIM4_CCR2 TIM_CCR2(TIM4)
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#define TIM5_CCR2 TIM_CCR2(TIM5)
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#define TIM8_CCR2 TIM_CCR2(TIM8)
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/* Capture/compare register 3 (TIMx_CCR3) */
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#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C)
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#define TIM1_CCR3 TIM_CCR3(TIM1)
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#define TIM2_CCR3 TIM_CCR3(TIM2)
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#define TIM3_CCR3 TIM_CCR3(TIM3)
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#define TIM4_CCR3 TIM_CCR3(TIM4)
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#define TIM5_CCR3 TIM_CCR3(TIM5)
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#define TIM8_CCR3 TIM_CCR3(TIM8)
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/* Capture/compare register 4 (TIMx_CCR4) */
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#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40)
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#define TIM1_CCR4 TIM_CCR4(TIM1)
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#define TIM2_CCR4 TIM_CCR4(TIM2)
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#define TIM3_CCR4 TIM_CCR4(TIM3)
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#define TIM4_CCR4 TIM_CCR4(TIM4)
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#define TIM5_CCR4 TIM_CCR4(TIM5)
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#define TIM8_CCR4 TIM_CCR4(TIM8)
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/* Break and dead-time register (TIMx_BDTR) */
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#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44)
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#define TIM1_BDTR TIM_BDTR(TIM1)
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#define TIM8_BDTR TIM_BDTR(TIM8)
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/* DMA control register (TIMx_DCR) */
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#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48)
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#define TIM1_DCR TIM_DCR(TIM1)
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#define TIM2_DCR TIM_DCR(TIM2)
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#define TIM3_DCR TIM_DCR(TIM3)
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#define TIM4_DCR TIM_DCR(TIM4)
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#define TIM5_DCR TIM_DCR(TIM5)
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#define TIM8_DCR TIM_DCR(TIM8)
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/* DMA address for full transfer (TIMx_DMAR) */
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#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C)
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#define TIM1_DMAR TIM_DMAR(TIM1)
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#define TIM2_DMAR TIM_DMAR(TIM2)
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#define TIM3_DMAR TIM_DMAR(TIM3)
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#define TIM4_DMAR TIM_DMAR(TIM4)
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#define TIM5_DMAR TIM_DMAR(TIM5)
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#define TIM8_DMAR TIM_DMAR(TIM8)
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/* --- TIMx_CR1 values ----------------------------------------------------- */
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/* CKD[1:0]: Clock division */
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#define TIM_CR1_CKD_CK_INT (0x0 << 8)
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#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)
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#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)
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#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)
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/* ARPE: Auto-reload preload enable */
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#define TIM_CR1_ARPE (1 << 7)
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/* CMS[1:0]: Center-aligned mode selection */
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#define TIM_CR1_CMS_EDGE (0x0 << 5)
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#define TIM_CR1_CMS_CENTER_1 (0x1 << 5)
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#define TIM_CR1_CMS_CENTER_2 (0x2 << 5)
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#define TIM_CR1_CMS_CENTER_3 (0x3 << 5)
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#define TIM_CR1_CMS_MASK (0x3 << 5)
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/* DIR: Direction */
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#define TIM_CR1_DIR_UP (0 << 4)
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#define TIM_CR1_DIR_DOWN (1 << 4)
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/* OPM: One pulse mode */
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#define TIM_CR1_OPM (1 << 3)
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/* URS: Update request source */
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#define TIM_CR1_URS (1 << 2)
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/* UDIS: Update disable */
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#define TIM_CR1_UDIS (1 << 1)
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/* CEN: Counter enable */
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#define TIM_CR1_CEN (1 << 0)
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/* --- TIMx_CR2 values ----------------------------------------------------- */
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/* OIS4: Output idle state 4 (OC4 output) */
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#define TIM_CR2_OIS4 (1 << 14)
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/* OIS3N: Output idle state 3 (OC3N output) */
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#define TIM_CR2_OIS3N (1 << 13)
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/* OIS3: Output idle state 3 (OC3 output) */
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#define TIM_CR2_OIS3 (1 << 12)
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/* OIS2N: Output idle state 2 (OC2N output) */
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#define TIM_CR2_OIS2N (1 << 11)
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/* OIS2: Output idle state 2 (OC2 output) */
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#define TIM_CR2_OIS2 (1 << 10)
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/* OIS1N: Output idle state 1 (OC1N output) */
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#define TIM_CR2_OIS1N (1 << 9)
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/* OIS1: Output idle state 1 (OC1 output) */
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#define TIM_CR2_OIS1 (1 << 8)
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#define TIM_CR2_OIS_MASK (0x7f << 8)
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/* TI1S: TI1 selection */
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#define TIM_CR2_TI1S (1 << 7)
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/* MMS[2:0]: Master mode selection */
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#define TIM_CR2_MMS_RESET (0x0 << 4)
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#define TIM_CR2_MMS_ENABLE (0x1 << 4)
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#define TIM_CR2_MMS_UPDATE (0x2 << 4)
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#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4)
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#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4)
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#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4)
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#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)
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#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)
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#define TIM_CR2_MMS_MASK (0x7 << 4)
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/* CCDS: Capture/compare DMA selection */
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#define TIM_CR2_CCDS (1 << 3)
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/* CCUS: Capture/compare control update selection */
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#define TIM_CR2_CCUS (1 << 2)
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/* CCPC: Capture/compare preload control */
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#define TIM_CR2_CCPC (1 << 0)
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/* --- TIMx_SMCR values ---------------------------------------------------- */
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/* ETP: External trigger polarity */
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#define TIM_SMCR_ETP (1 << 15)
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/* ECE: External clock enable */
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#define TIM_SMCR_ECE (1 << 14)
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/* ETPS[1:0]: External trigger prescaler */
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#define TIM_SMCR_ETPS_OFF (0x0 << 12)
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#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)
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#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)
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#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)
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#define TIM_SMCR_ETPS_MASK (0X3 << 12)
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/* ETF[3:0]: External trigger filter */
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#define TIM_SMCR_ETF_OFF (0x0 << 8)
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#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8)
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#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8)
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#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8)
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#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8)
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#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8)
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#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8)
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#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)
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#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)
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#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)
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#define TIM_SMCR_ETF_MASK (0xF << 8)
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/* MSM: Master/slave mode */
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#define TIM_SMCR_MSM (1 << 7)
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/* TS[2:0]: Trigger selection */
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#define TIM_SMCR_TS_ITR0 (0x0 << 4)
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#define TIM_SMCR_TS_ITR1 (0x1 << 4)
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#define TIM_SMCR_TS_ITR2 (0x2 << 4)
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#define TIM_SMCR_TS_ITR3 (0x3 << 4)
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#define TIM_SMCR_TS_IT1F_ED (0x4 << 4)
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#define TIM_SMCR_TS_IT1FP1 (0x5 << 4)
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#define TIM_SMCR_TS_IT1FP2 (0x6 << 4)
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#define TIM_SMCR_TS_ETRF (0x7 << 4)
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#define TIM_SMCR_TS_MASK (0x7 << 4)
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/* SMS[2:0]: Slave mode selection */
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#define TIM_SMCR_SMS_OFF (0x0 << 0)
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#define TIM_SMCR_SMS_EM1 (0x1 << 0)
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#define TIM_SMCR_SMS_EM2 (0x2 << 0)
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#define TIM_SMCR_SMS_EM3 (0x3 << 0)
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#define TIM_SMCR_SMS_RM (0x4 << 0)
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#define TIM_SMCR_SMS_GM (0x5 << 0)
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#define TIM_SMCR_SMS_TM (0x6 << 0)
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#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
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#define TIM_SMCR_SMS_MASK (0x7 << 0)
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/* --- TIMx_DIER values ---------------------------------------------------- */
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/* TDE: Trigger DMA request enable */
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#define TIM_DIER_TDE (1 << 14)
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/* COMDE: COM DMA request enable */
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#define TIM_DIER_COMDE (1 << 13)
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/* CC4DE: Capture/Compare 4 DMA request enable */
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#define TIM_DIER_CC4DE (1 << 12)
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/* CC3DE: Capture/Compare 3 DMA request enable */
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#define TIM_DIER_CC3DE (1 << 11)
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/* CC2DE: Capture/Compare 2 DMA request enable */
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#define TIM_DIER_CC2DE (1 << 10)
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/* CC1DE: Capture/Compare 1 DMA request enable */
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#define TIM_DIER_CC1DE (1 << 9)
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/* UDE: Update DMA request enable */
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#define TIM_DIER_UDE (1 << 8)
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/* BIE: Break interrupt enable */
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#define TIM_DIER_BIE (1 << 7)
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/* TIE: Trigger interrupt enable */
|
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#define TIM_DIER_TIE (1 << 6)
|
|
|
|
/* COMIE: COM interrupt enable */
|
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#define TIM_DIER_COMIE (1 << 5)
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|
|
|
/* CC4IE: Capture/compare 4 interrupt enable */
|
|
#define TIM_DIER_CC4IE (1 << 4)
|
|
|
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/* CC3IE: Capture/compare 3 interrupt enable */
|
|
#define TIM_DIER_CC3IE (1 << 3)
|
|
|
|
/* CC2IE: Capture/compare 2 interrupt enable */
|
|
#define TIM_DIER_CC2IE (1 << 2)
|
|
|
|
/* CC1IE: Capture/compare 1 interrupt enable */
|
|
#define TIM_DIER_CC1IE (1 << 1)
|
|
|
|
/* UIE: Update interrupt enable */
|
|
#define TIM_DIER_UIE (1 << 0)
|
|
|
|
/* --- TIMx_SR values ------------------------------------------------------ */
|
|
|
|
/* CC4OF: Capture/compare 4 overcapture flag */
|
|
#define TIM_SR_CC4OF (1 << 12)
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|
|
|
/* CC3OF: Capture/compare 3 overcapture flag */
|
|
#define TIM_SR_CC3OF (1 << 11)
|
|
|
|
/* CC2OF: Capture/compare 2 overcapture flag */
|
|
#define TIM_SR_CC2OF (1 << 10)
|
|
|
|
/* CC1OF: Capture/compare 1 overcapture flag */
|
|
#define TIM_SR_CC1OF (1 << 9)
|
|
|
|
/* BIF: Break interrupt flag */
|
|
#define TIM_SR_BIF (1 << 7)
|
|
|
|
/* TIF: Trigger interrupt flag */
|
|
#define TIM_SR_TIF (1 << 6)
|
|
|
|
/* COMIF: COM interrupt flag */
|
|
#define TIM_SR_COMIF (1 << 5)
|
|
|
|
/* CC4IF: Capture/compare 4 interrupt flag */
|
|
#define TIM_SR_CC4IF (1 << 4)
|
|
|
|
/* CC3IF: Capture/compare 3 interrupt flag */
|
|
#define TIM_SR_CC3IF (1 << 3)
|
|
|
|
/* CC2IF: Capture/compare 2 interrupt flag */
|
|
#define TIM_SR_CC2IF (1 << 2)
|
|
|
|
/* CC1IF: Capture/compare 1 interrupt flag */
|
|
#define TIM_SR_CC1IF (1 << 1)
|
|
|
|
/* UIF: Update interrupt flag */
|
|
#define TIM_SR_UIF (1 << 0)
|
|
|
|
/* --- TIMx_EGR values ----------------------------------------------------- */
|
|
|
|
/* BG: Break generation */
|
|
#define TIM_EGR_BG (1 << 7)
|
|
|
|
/* TG: Trigger generation */
|
|
#define TIM_EGR_TG (1 << 6)
|
|
|
|
/* COMG: Capture/compare control update generation */
|
|
#define TIM_EGR_COMG (1 << 5)
|
|
|
|
/* CC4G: Capture/compare 4 generation */
|
|
#define TIM_EGR_CC4G (1 << 4)
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|
|
|
/* CC3G: Capture/compare 3 generation */
|
|
#define TIM_EGR_CC3G (1 << 3)
|
|
|
|
/* CC2G: Capture/compare 2 generation */
|
|
#define TIM_EGR_CC2G (1 << 2)
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|
|
|
/* CC1G: Capture/compare 1 generation */
|
|
#define TIM_EGR_CC1G (1 << 1)
|
|
|
|
/* UG: Update generation */
|
|
#define TIM_EGR_UG (1 << 0)
|
|
|
|
/* --- TIMx_CCMR1 values --------------------------------------------------- */
|
|
|
|
/* --- Output compare mode --- */
|
|
|
|
/* OC2CE: Output compare 2 clear enable */
|
|
#define TIM_CCMR1_OC2CE (1 << 15)
|
|
|
|
/* OC2M[2:0]: Output compare 2 mode */
|
|
#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12)
|
|
#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12)
|
|
#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12)
|
|
#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12)
|
|
#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12)
|
|
#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)
|
|
#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12)
|
|
#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12)
|
|
#define TIM_CCMR1_OC2M_MASK (0x7 << 12)
|
|
|
|
/* OC2PE: Output compare 2 preload enable */
|
|
#define TIM_CCMR1_OC2PE (1 << 11)
|
|
|
|
/* OC2FE: Output compare 2 fast enable */
|
|
#define TIM_CCMR1_OC2FE (1 << 10)
|
|
|
|
/* CC2S[1:0]: Capture/compare 2 selection */
|
|
/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
|
|
* TIMx_CCER). */
|
|
#define TIM_CCMR1_CC2S_OUT (0x0 << 8)
|
|
#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)
|
|
#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)
|
|
#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)
|
|
#define TIM_CCMR1_CC2S_MASK (0x3 << 8)
|
|
|
|
/* OC1CE: Output compare 1 clear enable */
|
|
#define TIM_CCMR1_OC1CE (1 << 7)
|
|
|
|
/* OC1M[2:0]: Output compare 1 mode */
|
|
#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4)
|
|
#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4)
|
|
#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4)
|
|
#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4)
|
|
#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4)
|
|
#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)
|
|
#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4)
|
|
#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4)
|
|
#define TIM_CCMR1_OC1M_MASK (0x7 << 4)
|
|
|
|
/* OC1PE: Output compare 1 preload enable */
|
|
#define TIM_CCMR1_OC1PE (1 << 3)
|
|
|
|
/* OC1FE: Output compare 1 fast enable */
|
|
#define TIM_CCMR1_OC1FE (1 << 2)
|
|
|
|
/* CC1S[1:0]: Capture/compare 1 selection */
|
|
/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
|
|
* TIMx_CCER). */
|
|
#define TIM_CCMR1_CC1S_OUT (0x0 << 0)
|
|
#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0)
|
|
#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0)
|
|
#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)
|
|
#define TIM_CCMR1_CC1S_MASK (0x3 << 0)
|
|
|
|
/* --- Input capture mode --- */
|
|
|
|
/* IC2F[3:0]: Input capture 2 filter */
|
|
#define TIM_CCMR1_IC2F_OFF (0x0 << 12)
|
|
#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12)
|
|
#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12)
|
|
#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)
|
|
#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)
|
|
#define TIM_CCMR1_IC2F_MASK (0xF << 12)
|
|
|
|
/* IC2PSC[1:0]: Input capture 2 prescaler */
|
|
#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10)
|
|
#define TIM_CCMR1_IC2PSC_2 (0x1 << 10)
|
|
#define TIM_CCMR1_IC2PSC_4 (0x2 << 10)
|
|
#define TIM_CCMR1_IC2PSC_8 (0x3 << 10)
|
|
#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10)
|
|
|
|
/* IC1F[3:0]: Input capture 1 filter */
|
|
#define TIM_CCMR1_IC1F_OFF (0x0 << 4)
|
|
#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4)
|
|
#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4)
|
|
#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)
|
|
#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)
|
|
#define TIM_CCMR1_IC1F_MASK (0xF << 4)
|
|
|
|
/* IC1PSC[1:0]: Input capture 1 prescaler */
|
|
#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2)
|
|
#define TIM_CCMR1_IC1PSC_2 (0x1 << 2)
|
|
#define TIM_CCMR1_IC1PSC_4 (0x2 << 2)
|
|
#define TIM_CCMR1_IC1PSC_8 (0x3 << 2)
|
|
#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2)
|
|
|
|
/* --- TIMx_CCMR2 values --------------------------------------------------- */
|
|
|
|
/* --- Output compare mode --- */
|
|
|
|
/* OC4CE: Output compare 4 clear enable */
|
|
#define TIM_CCMR2_OC4CE (1 << 15)
|
|
|
|
/* OC4M[2:0]: Output compare 4 mode */
|
|
#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12)
|
|
#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12)
|
|
#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12)
|
|
#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12)
|
|
#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12)
|
|
#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)
|
|
#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12)
|
|
#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12)
|
|
#define TIM_CCMR2_OC4M_MASK (0x7 << 12)
|
|
|
|
/* OC4PE: Output compare 4 preload enable */
|
|
#define TIM_CCMR2_OC4PE (1 << 11)
|
|
|
|
/* OC4FE: Output compare 4 fast enable */
|
|
#define TIM_CCMR2_OC4FE (1 << 10)
|
|
|
|
/* CC4S[1:0]: Capture/compare 4 selection */
|
|
/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
|
|
* TIMx_CCER). */
|
|
#define TIM_CCMR2_CC4S_OUT (0x0 << 8)
|
|
#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8)
|
|
#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8)
|
|
#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)
|
|
#define TIM_CCMR2_CC4S_MASK (0x3 << 8)
|
|
|
|
/* OC3CE: Output compare 3 clear enable */
|
|
#define TIM_CCMR2_OC3CE (1 << 7)
|
|
|
|
/* OC3M[2:0]: Output compare 3 mode */
|
|
#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4)
|
|
#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4)
|
|
#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4)
|
|
#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4)
|
|
#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4)
|
|
#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)
|
|
#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4)
|
|
#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4)
|
|
#define TIM_CCMR2_OC3M_MASK (0x7 << 4)
|
|
|
|
/* OC3PE: Output compare 3 preload enable */
|
|
#define TIM_CCMR2_OC3PE (1 << 3)
|
|
|
|
/* OC3FE: Output compare 3 fast enable */
|
|
#define TIM_CCMR2_OC3FE (1 << 2)
|
|
|
|
/* CC3S[1:0]: Capture/compare 3 selection */
|
|
/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
|
|
* TIMx_CCER). */
|
|
#define TIM_CCMR2_CC3S_OUT (0x0 << 0)
|
|
#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0)
|
|
#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0)
|
|
#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0)
|
|
#define TIM_CCMR2_CC3S_MASK (0x3 << 0)
|
|
|
|
/* --- Input capture mode --- */
|
|
|
|
/* IC4F[3:0]: Input capture 4 filter */
|
|
#define TIM_CCMR2_IC4F_OFF (0x0 << 12)
|
|
#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12)
|
|
#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12)
|
|
#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)
|
|
#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)
|
|
#define TIM_CCMR2_IC4F_MASK (0xF << 12)
|
|
|
|
/* IC4PSC[1:0]: Input capture 4 prescaler */
|
|
#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10)
|
|
#define TIM_CCMR2_IC4PSC_2 (0x1 << 10)
|
|
#define TIM_CCMR2_IC4PSC_4 (0x2 << 10)
|
|
#define TIM_CCMR2_IC4PSC_8 (0x3 << 10)
|
|
#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10)
|
|
|
|
/* IC3F[3:0]: Input capture 3 filter */
|
|
#define TIM_CCMR2_IC3F_OFF (0x0 << 4)
|
|
#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4)
|
|
#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4)
|
|
#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)
|
|
#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)
|
|
#define TIM_CCMR2_IC3F_MASK (0xF << 4)
|
|
|
|
/* IC3PSC[1:0]: Input capture 3 prescaler */
|
|
#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2)
|
|
#define TIM_CCMR2_IC3PSC_2 (0x1 << 2)
|
|
#define TIM_CCMR2_IC3PSC_4 (0x2 << 2)
|
|
#define TIM_CCMR2_IC3PSC_8 (0x3 << 2)
|
|
#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2)
|
|
|
|
/* --- TIMx_CCER values ---------------------------------------------------- */
|
|
|
|
/* CC4P: Capture/compare 4 output polarity */
|
|
#define TIM_CCER_CC4P (1 << 13)
|
|
|
|
/* CC4E: Capture/compare 4 output enable */
|
|
#define TIM_CCER_CC4E (1 << 12)
|
|
|
|
/* CC3NP: Capture/compare 3 complementary output polarity */
|
|
#define TIM_CCER_CC3NP (1 << 11)
|
|
|
|
/* CC3NE: Capture/compare 3 complementary output enable */
|
|
#define TIM_CCER_CC3NE (1 << 10)
|
|
|
|
/* CC3P: Capture/compare 3 output polarity */
|
|
#define TIM_CCER_CC3P (1 << 9)
|
|
|
|
/* CC3E: Capture/compare 3 output enable */
|
|
#define TIM_CCER_CC3E (1 << 8)
|
|
|
|
/* CC2NP: Capture/compare 2 complementary output polarity */
|
|
#define TIM_CCER_CC2NP (1 << 7)
|
|
|
|
/* CC2NE: Capture/compare 2 complementary output enable */
|
|
#define TIM_CCER_CC2NE (1 << 6)
|
|
|
|
/* CC2P: Capture/compare 2 output polarity */
|
|
#define TIM_CCER_CC2P (1 << 5)
|
|
|
|
/* CC2E: Capture/compare 2 output enable */
|
|
#define TIM_CCER_CC2E (1 << 4)
|
|
|
|
/* CC1NP: Capture/compare 1 complementary output polarity */
|
|
#define TIM_CCER_CC1NP (1 << 3)
|
|
|
|
/* CC1NE: Capture/compare 1 complementary output enable */
|
|
#define TIM_CCER_CC1NE (1 << 2)
|
|
|
|
/* CC1P: Capture/compare 1 output polarity */
|
|
#define TIM_CCER_CC1P (1 << 1)
|
|
|
|
/* CC1E: Capture/compare 1 output enable */
|
|
#define TIM_CCER_CC1E (1 << 0)
|
|
|
|
/* --- TIMx_CNT values ----------------------------------------------------- */
|
|
|
|
/* CNT[15:0]: Counter value */
|
|
|
|
/* --- TIMx_PSC values ----------------------------------------------------- */
|
|
|
|
/* PSC[15:0]: Prescaler value */
|
|
|
|
/* --- TIMx_ARR values ----------------------------------------------------- */
|
|
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/* ARR[15:0]: Prescaler value */
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/* --- TIMx_RCR values ----------------------------------------------------- */
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/* REP[15:0]: Repetition counter value */
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/* --- TIMx_CCR1 values ---------------------------------------------------- */
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/* CCR1[15:0]: Capture/compare 1 value */
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/* --- TIMx_CCR2 values ---------------------------------------------------- */
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/* CCR2[15:0]: Capture/compare 2 value */
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/* --- TIMx_CCR3 values ---------------------------------------------------- */
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/* CCR3[15:0]: Capture/compare 3 value */
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/* --- TIMx_CCR4 values ---------------------------------------------------- */
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/* CCR4[15:0]: Capture/compare 4 value */
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/* --- TIMx_BDTR values ---------------------------------------------------- */
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/* MOE: Main output enable */
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#define TIM_BDTR_MOE (1 << 15)
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/* AOE: Automatic output enable */
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#define TIM_BDTR_AOE (1 << 14)
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/* BKP: Break polarity */
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#define TIM_BDTR_BKP (1 << 13)
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/* BKE: Break enable */
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#define TIM_BDTR_BKE (1 << 12)
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/* OSSR: Off-state selection of run mode */
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#define TIM_BDTR_OSSR (1 << 11)
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/* OSSI: Off-state selection of idle mode */
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#define TIM_BDTR_OSSI (1 << 10)
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/* LOCK[1:0]: Lock configuration */
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#define TIM_BDTR_LOCK_OFF (0x0 << 8)
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#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)
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#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)
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#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)
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#define TIM_BDTR_LOCK_MASK (0x3 << 8)
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/* DTG[7:0]: Dead-time generator set-up */
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#define TIM_BDTR_DTG_MASK 0x00FF
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/* --- TIMx_DCR values ----------------------------------------------------- */
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/* DBL[4:0]: DMA burst length */
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#define TIM_BDTR_DBL_MASK (0x1F << 8)
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/* DBA[4:0]: DMA base address */
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#define TIM_BDTR_DBA_MASK (0x1F << 0)
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/* --- TIMx_DMAR values ---------------------------------------------------- */
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/* DMAB[15:0]: DMA register for burst accesses */
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/* --- TIMx convenience defines -------------------------------------------- */
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/* Capture Compare channel designators */
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enum tim_oc_id {
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TIM_OC1=0,
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TIM_OC1N,
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TIM_OC2,
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TIM_OC2N,
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TIM_OC3,
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TIM_OC3N,
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TIM_OC4,
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};
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/* --- TIM functions ------------------------------------------------------- */
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void timer_set_mode(u32 timer_peripheral, u8 clock_div,
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u8 alignment, u8 direction);
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void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
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void timer_enable_preload(u32 timer_peripheral);
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void timer_disable_preload(u32 timer_peripheral);
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void timer_set_alignment(u32 timer_peripheral, u32 alignment);
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void timer_direction_up(u32 timer_peripheral);
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void timer_direction_down(u32 timer_peripheral);
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void timer_one_shot_mode(u32 timer_peripheral);
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void timer_continuous_mode(u32 timer_peripheral);
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void timer_update_on_any(u32 timer_peripheral);
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void timer_update_on_overflow(u32 timer_peripheral);
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void timer_enable_update_event(u32 timer_peripheral);
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void timer_disable_update_event(u32 timer_peripheral);
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void timer_enable_counter(u32 timer_peripheral);
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void timer_disable_counter(u32 timer_peripheral);
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void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs);
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void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs);
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void timer_set_ti1_ch123_xor(u32 timer_peripheral);
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void timer_set_ti1_ch1(u32 timer_peripheral);
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void timer_set_master_mode(u32 timer_peripheral, u32 mode);
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void timer_set_dma_on_compare_event(u32 timer_peripheral);
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void timer_set_dma_on_update_event(u32 timer_peripheral);
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void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral);
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void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral);
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void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral);
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void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral);
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void timer_set_period(u32 timer_peripheral, u32 period);
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void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, u32 mode);
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void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id);
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void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value);
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#endif
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