201 lines
5.1 KiB
C
201 lines
5.1 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/timer.h>
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void clock_setup(void)
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{
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rcc_clock_setup_in_hse_8mhz_out_72mhz();
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/* Enable TIM1 clock. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
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/* Enable GPIOA, GPIOB and Alternate Function clocks. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR,
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RCC_APB2ENR_IOPAEN |
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RCC_APB2ENR_IOPBEN |
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RCC_APB2ENR_AFIOEN);
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}
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void gpio_setup(void)
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{
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/*
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* Set GPIO12 (PORTC) (led) to
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* 'output alternate function push-pull'.
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*/
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gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
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/*
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* Set TIM1 chanel output pins to
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* 'output alternate function push-pull'.
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*/
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gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
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GPIO_TIM1_CH1 |
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GPIO_TIM1_CH2 |
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GPIO_TIM1_CH3);
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/*
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* Set TIM1 complementary chanel output pins to
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* 'output alternate function push-pull'.
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*/
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gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
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GPIO_TIM1_CH1N |
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GPIO_TIM1_CH2N |
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GPIO_TIM1_CH3N);
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}
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void tim_setup(void)
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{
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/* Enable TIM1 commutation interrupt. */
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nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ);
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/* Clock division. */
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timer_set_clock_division(TIM1, TIM_CR1_CKD_CK_INT);
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/* Timer global mode:
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* - No divider
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* - alignment edge
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* - direction up
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*/
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timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
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TIM_CR1_CMS_EDGE,
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TIM_CR1_DIR_UP);
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/* Enable preload. */
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timer_enable_preload(TIM1);
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/* Continous mode. */
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timer_continuous_mode(TIM1);
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/* Period (32kHz) */
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timer_set_period(TIM1, 72000000 / 32000);
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/* -- OC1 and OC1N configuration -- */
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC1);
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timer_disable_oc_output(TIM1, TIM_OC1N);
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/* Configure global mode of line 1. */
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timer_disable_oc_clear(TIM1, TIM_OC1);
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timer_enable_oc_preload(TIM1, TIM_OC1);
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timer_set_oc_slow_mode(TIM1, TIM_OC1);
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_CCMR1_OC1M_PWM1);
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/* Configure OC1. */
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timer_set_oc_polarity_high(TIM1, TIM_OC1);
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timer_set_oc_idle_state_set(TIM1, TIM_OC1);
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/* Configure OC1N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC1N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC1N);
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/* Set the capture compare value for OC1. */
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timer_set_oc_value(TIM1, TIM_OC1, 100);
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC1);
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timer_enable_oc_output(TIM1, TIM_OC1N);
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/* -- OC2 and OC2N configuration -- */
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC2);
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timer_disable_oc_output(TIM1, TIM_OC2N);
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/* Configure global mode of line 2. */
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timer_disable_oc_clear(TIM1, TIM_OC2);
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timer_enable_oc_preload(TIM1, TIM_OC2);
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timer_set_oc_slow_mode(TIM1, TIM_OC2);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_CCMR1_OC2M_PWM1);
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/* Configure OC2. */
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timer_set_oc_polarity_high(TIM1, TIM_OC2);
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timer_set_oc_idle_state_set(TIM1, TIM_OC2);
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/* Configure OC2N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC2N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC2N);
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/* Set the capture compare value for OC1. */
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timer_set_oc_value(TIM1, TIM_OC2, 200);
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC2);
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timer_enable_oc_output(TIM1, TIM_OC2N);
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/* -- OC3 and OC3N configuration -- */
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC3);
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timer_disable_oc_output(TIM1, TIM_OC3N);
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/* Configure global mode of line 3. */
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timer_disable_oc_clear(TIM1, TIM_OC3);
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timer_enable_oc_preload(TIM1, TIM_OC3);
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timer_set_oc_slow_mode(TIM1, TIM_OC3);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_CCMR2_OC3M_PWM1);
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/* Configure OC3. */
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timer_set_oc_polarity_high(TIM1, TIM_OC3);
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timer_set_oc_idle_state_set(TIM1, TIM_OC3);
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/* Configure OC3N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC3N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC3N);
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/* Set the capture compare value for OC3. */
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timer_set_oc_value(TIM1, TIM_OC3, 300);
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC3);
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timer_enable_oc_output(TIM1, TIM_OC3N);
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/* ---- */
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/* ARR reload enable */
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timer_enable_preload(TIM1);
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/* Enable outputs in the break subsystem */
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TIM1_BDTR |= TIM_BDTR_MOE;
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/* Counter enable */
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timer_enable_counter(TIM1);
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}
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int main(void)
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{
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clock_setup();
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gpio_setup();
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tim_setup();
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while (1) {
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__asm("nop");
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}
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return 0;
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}
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