377 lines
7.4 KiB
C
377 lines
7.4 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Basic ADC handling API.
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*
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* Examples:
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* rcc_peripheral_enable_clock(&RCC_APB2ENR, ADC1EN);
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* rcc_peripheral_disable_clock(&RCC_APB2ENR, ADC1EN);
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* rcc_peripheral_reset(&RCC_APB2RSTR, ADC1RST);
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* rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST);
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*
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* rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2);
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* adc_set_mode(ADC1, TODO);
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* reg16 = adc_read(ADC1, ADC_CH_0);
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*/
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#include <libopenstm32/adc.h>
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void rcc_set_adc_clk(u32 prescaler)
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{
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/* TODO */
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/* FIXME: QUICK HACK to prevent compiler warnings. */
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prescaler = prescaler;
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}
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void adc_set_mode(u32 block, /* TODO */ u8 mode)
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{
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/* TODO */
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/* FIXME: QUICK HACK to prevent compiler warnings. */
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block = block;
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mode = mode;
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}
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void adc_read(u32 block, u32 channel)
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{
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/* TODO */
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/* FIXME: QUICK HACK to prevent compiler warnings. */
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block = block;
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channel = channel;
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}
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void adc_enable_analog_watchdog_regular(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_AWDEN;
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}
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void adc_disable_analog_watchdog_regular(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
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}
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void adc_enable_analog_watchdog_injected(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JAWDEN;
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}
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void adc_disable_analog_watchdog_injected(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
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}
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void adc_enable_discontinous_mode_regular(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_DISCEN;
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}
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void adc_disable_discontinous_mode_regular(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
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}
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void adc_enable_discontinous_mode_injected(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JDISCEN;
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}
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void adc_disable_discontinous_mode_injected(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
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}
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void adc_enable_automatic_injected_group_conversion(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JAUTO;
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}
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void adc_disable_automatic_injected_group_conversion(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
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}
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void adc_enable_analog_watchdog_on_all_channels(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_AWDSGL;
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}
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void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
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{
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u32 reg32;
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reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */
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if (channel < 18)
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reg32 |= channel;
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ADC_CR1(adc) = reg32;
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ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
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}
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void adc_enable_scan_mode(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_SCAN;
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}
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void adc_disable_scan_mode(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_SCAN;
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}
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void adc_enable_jeoc_interrupt(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_JEOCIE;
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}
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void adc_disable_jeoc_interrupt(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
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}
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void adc_enable_awd_interrupt(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_AWDIE;
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}
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void adc_disable_awd_interrupt(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
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}
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void adc_enable_eoc_interrupt(u32 adc)
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{
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ADC_CR1(adc) |= ADC_CR1_EOCIE;
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}
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void adc_disable_eoc_interrupt(u32 adc)
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{
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ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
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}
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void adc_enable_temperature_sensor(u32 adc)
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{
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ADC_CR2(adc) |= ADC_CR2_TSVREFE;
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}
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void adc_disable_temperature_sensor(u32 adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
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}
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void adc_start_conversion_regular(u32 adc)
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{
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/* start conversion on regular channels */
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ADC_CR2(adc) |= ADC_CR2_SWSTART;
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/* wait til the ADC starts the conversion */
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while (ADC_CR2(adc) & ADC_CR2_SWSTART);
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}
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void adc_start_conversion_injected(u32 adc)
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{
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/* start conversion on injected channels */
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ADC_CR2(adc) |= ADC_CR2_JSWSTART;
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/* wait til the ADC starts the conversion */
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while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
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}
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void adc_enable_external_trigger_regular(u32 adc, u8 trigger)
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{
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u32 reg32;
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reg32 = (ADC_CR2(adc) & 0xfff1ffff); /* Clear bits [19:17]. */
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if (trigger < 8)
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reg32 |= (trigger << ADC_CR2_EXTSEL_LSB);
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ADC_CR2(adc) = reg32;
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ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
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}
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void adc_disable_external_trigger_regular(u32 adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
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}
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void adc_enable_external_trigger_injected(u32 adc, u8 trigger)
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{
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u32 reg32;
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reg32 = (ADC_CR2(adc) & 0xffff8fff); /* Clear bits [12:14]. */
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if (trigger < 8)
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reg32 |= (trigger << ADC_CR2_JEXTSEL_LSB);
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ADC_CR2(adc) = reg32;
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ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
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}
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void adc_disable_external_trigger_injected(u32 adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
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}
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void adc_set_left_aligned(u32 adc)
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{
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ADC_CR2(adc) |= ADC_CR2_ALIGN;
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}
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void adc_set_right_aligned(u32 adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
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}
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void adc_enable_dma(u32 adc)
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{
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if ((adc == ADC1) | (adc==ADC3))
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ADC_CR2(adc) |= ADC_CR2_DMA;
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}
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void adc_disable_dma(u32 adc)
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{
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if ((adc == ADC1) | (adc==ADC3))
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ADC_CR2(adc) &= ~ADC_CR2_DMA;
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}
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void adc_reset_calibration(u32 adc)
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{
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ADC_CR2(adc) |= ADC_CR2_RSTCAL;
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while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
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}
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void adc_calibration(u32 adc)
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{
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ADC_CR2(adc) |= ADC_CR2_CAL;
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while (ADC_CR2(adc) & ADC_CR2_CAL);
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}
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void adc_set_continous_conversion_mode(u32 adc)
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{
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ADC_CR2(adc) |= ADC_CR2_CONT;
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}
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void adc_set_single_conversion_mode(u32 adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_CONT;
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}
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void adc_on(u32 adc)
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{
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ADC_CR2(adc) |= ADC_CR2_ADON;
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}
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void adc_off(u32 adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_ADON;
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}
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void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
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{
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u32 reg32;
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if (channel < 10) {
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reg32 = ADC_SMPR2(adc);
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reg32 &= ~(0b111 << (channel * 3));
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reg32 |= (time << (channel *3));
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ADC_SMPR2(adc) = reg32;
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}
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else {
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reg32 = ADC_SMPR1(adc);
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reg32 &= ~(0b111 << ((channel-10) *3));
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reg32 |= (time << ((channel-10) *3));
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ADC_SMPR1(adc) = reg32;
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}
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}
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void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
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{
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u32 reg32 = 0;
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u8 i;
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for (i=0; i<=9; i++) {
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reg32 |= (time << (i * 3));
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}
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ADC_SMPR2(adc) = reg32;
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for (i=10; i<=17; i++) {
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reg32 |= (time << ((i-10) * 3));
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}
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ADC_SMPR1(adc) = reg32;
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}
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void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
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{
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u32 reg32 = 0;
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reg32 = (u32)threshold;
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reg32 &= ~0xfffff000; /* clear all bits above 11 */
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ADC_HTR(adc) = reg32;
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}
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void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
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{
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u32 reg32 = 0;
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reg32 = (u32)threshold;
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reg32 &= ~0xfffff000; /* clear all bits above 11 */
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ADC_LTR(adc) = reg32;
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}
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void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
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{
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u32 reg32_1 = 0;
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u32 reg32_2 = 0;
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u32 reg32_3 = 0;
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u8 i = 0;
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/* maximum sequence length is 16 channels */
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if (length > 16)
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return;
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for (i=1; i<=length; i++) {
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if (i<=6)
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reg32_3 |= (channel[i-1] << ((i-1) * 5));
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if ((i>6) & (i<=12))
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reg32_2 |= (channel[i-6-1] << ((i-6-1) * 5));
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if ((i>12) & (i<=16))
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reg32_1 |= (channel[i-12-1] << ((i-12-1) * 5));
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}
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reg32_1 |= (length << ADC_SQR1_L_LSB);
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ADC_SQR1(adc) = reg32_1;
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ADC_SQR2(adc) = reg32_2;
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ADC_SQR3(adc) = reg32_3;
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}
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void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
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{
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u32 reg32 = 0;
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u8 i = 0;
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/* maximum sequence length is 4 channels */
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if (length > 4)
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return;
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for (i=1; i<=length; i++) {
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reg32 |= (channel[i-1] << ((i-1) * 5));
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}
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reg32 |= (length << ADC_JSQR_JL_LSB);
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ADC_JSQR(adc) = reg32;
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}
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