278 lines
8.1 KiB
C
278 lines
8.1 KiB
C
/** @addtogroup dac_defines
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@author @htmlonly © @endhtmlonly 2012
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Felix Held <felix-libopencm3@felixheld.de>
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@author @htmlonly © @endhtmlonly 2020
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Ben Brewer <ben.brewer@codethink.co.uk>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
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* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
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The order of header inclusion is important. dac.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_DAC_H
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/** @endcond */
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#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
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#define LIBOPENCM3_DAC_COMMON_ALL_H
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/**@defgroup dac_registers DAC Registers
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@{*/
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/** DAC control register (DAC_CR) */
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#define DAC_CR(dac) MMIO32((dac) + 0x00)
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/** DAC software trigger register (DAC_SWTRIGR) */
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#define DAC_SWTRIGR(dac) MMIO32((dac) + 0x04)
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/** DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
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#define DAC_DHR12R1(dac) MMIO32((dac) + 0x08)
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/** DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
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#define DAC_DHR12L1(dac) MMIO32((dac) + 0x0C)
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/** DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
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#define DAC_DHR8R1(dac) MMIO32((dac) + 0x10)
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/** DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
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#define DAC_DHR12R2(dac) MMIO32((dac) + 0x14)
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/** DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
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#define DAC_DHR12L2(dac) MMIO32((dac) + 0x18)
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/** DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
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#define DAC_DHR8R2(dac) MMIO32((dac) + 0x1C)
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/** Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
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#define DAC_DHR12RD(dac) MMIO32((dac) + 0x20)
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/** DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
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#define DAC_DHR12LD(dac) MMIO32((dac) + 0x24)
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/** DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
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#define DAC_DHR8RD(dac) MMIO32((dac) + 0x28)
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/** DAC channel1 data output register (DAC_DOR1) */
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#define DAC_DOR1(dac) MMIO32((dac) + 0x2C)
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/** DAC channel2 data output register (DAC_DOR2) */
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#define DAC_DOR2(dac) MMIO32((dac) + 0x30)
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/** DAC status register.
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* @note not available on F1
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*/
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#define DAC_SR(dac) MMIO32((dac) + 0x34)
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/**@}*/
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/** @defgroup dac_cr_values DAC_CR values
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* @{
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*/
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/** DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
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* @note doesn't exist in most members of the STM32F1 family
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*/
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#define DAC_CR_DMAUDRIE2 (1 << 29)
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/** DMAEN2: DAC channel2 DMA enable */
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#define DAC_CR_DMAEN2 (1 << 28)
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/** MAMP2[3:0]: DAC channel2 mask/amplitude selector */
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#define DAC_CR_MAMP2_SHIFT 24
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/** WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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#define DAC_CR_WAVE2_SHIFT 22
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#define DAC_CR_WAVE2_MASK 0x3
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/** EN2: DAC channel2 enable */
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#define DAC_CR_EN2 (1 << 16)
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/** DMAUDRIE1: DAC channel1 DMA underrun interrupt enable
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* @note doesn't exist in most members of the STM32F1 family
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*/
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#define DAC_CR_DMAUDRIE1 (1 << 13)
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/** DMAEN1: DAC channel1 DMA enable */
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#define DAC_CR_DMAEN1 (1 << 12)
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/** MAMP1[3:0]: DAC channel1 mask/amplitude selector */
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#define DAC_CR_MAMP1_SHIFT 8
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/** WAVEn[1:0]: DAC channel1 noise/triangle wave generation enable */
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#define DAC_CR_WAVE1_SHIFT 6
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#define DAC_CR_WAVE1_MASK 0x3
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/** EN1: DAC channel1 enable */
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#define DAC_CR_EN1 (1 << 0)
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/**@}*/
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/**@defgroup dac_swtrigr_values DAC_SWTRIGR Values
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* @{
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*/
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/** SWTRIG2: DAC channel2 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
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/** SWTRIG1: DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
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/**@}*/
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/**@defgroup dac_dhrxxx_values DAC_DHRxxx Values
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* @{
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*/
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/* --- DAC_DHR12R1 values -------------------------------------------------- */
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#define DAC_DHR12R1_DACC1DHR_SHIFT 0
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#define DAC_DHR12R1_DACC1DHR_MASK 0xFFF
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/* --- DAC_DHR12L1 values -------------------------------------------------- */
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#define DAC_DHR12L1_DACC1DHR_SHIFT 4
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#define DAC_DHR12L1_DACC1DHR_MASK 0xFFF
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/* --- DAC_DHR8R1 values --------------------------------------------------- */
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#define DAC_DHR8R1_DACC1DHR_SHIFT 0
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#define DAC_DHR8R1_DACC1DHR_MASK 0xFF
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/* --- DAC_DHR12R2 values -------------------------------------------------- */
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#define DAC_DHR12R2_DACC2DHR_SHIFT 0
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#define DAC_DHR12R2_DACC2DHR_MASK 0xFFF
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/* --- DAC_DHR12L2 values -------------------------------------------------- */
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#define DAC_DHR12L2_DACC2DHR_SHIFT 4
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#define DAC_DHR12L2_DACC2DHR_MASK 0xFFF
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/* --- DAC_DHR8R2 values --------------------------------------------------- */
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#define DAC_DHR8R2_DACC2DHR_SHIFT 0
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#define DAC_DHR8R2_DACC2DHR_MASK 0xFF
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/* --- DAC_DHR12RD values -------------------------------------------------- */
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#define DAC_DHR12RD_DACC2DHR_SHIFT 16
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#define DAC_DHR12RD_DACC2DHR_MASK 0xFFF
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#define DAC_DHR12RD_DACC1DHR_SHIFT 0
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#define DAC_DHR12RD_DACC1DHR_MSK 0xFFF
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/* --- DAC_DHR12LD values -------------------------------------------------- */
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#define DAC_DHR12LD_DACC2DHR_SHIFT 16
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#define DAC_DHR12LD_DACC2DHR_MSK 0xFFF
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#define DAC_DHR12LD_DACC1DHR_SHIFT 0
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#define DAC_DHR12LD_DACC1DHR_MSK 0xFFF
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/* --- DAC_DHR8RD values --------------------------------------------------- */
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#define DAC_DHR8RD_DACC2DHR_SHIFT 8
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#define DAC_DHR8RD_DACC2DHR_MSK 0xFF
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#define DAC_DHR8RD_DACC1DHR_SHIFT 0
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#define DAC_DHR8RD_DACC1DHR_MSK 0xFF
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/**@}*/
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/**@defgroup dac_dorx_values DAC_DORx Values
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* @{
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*/
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/* --- DAC_DOR1 values ----------------------------------------------------- */
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#define DAC_DOR1_DACC1DOR_SHIFT 0
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#define DAC_DOR1_DACC1DOR_MSK 0xFFF
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/* --- DAC_DOR2 values ----------------------------------------------------- */
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#define DAC_DOR2_DACC2DOR_SHIFT 0
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#define DAC_DOR2_DACC2DOR_MSK 0xFFF
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/**@}*/
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/**@defgroup dac_sr_values DAC_SR Values
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* @{
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*/
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/** DAC channel 1 DMA underrun flag */
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#define DAC_SR_DMAUDR1 (1 << 13)
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/** DAC channel 2 DMA underrun flag */
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#define DAC_SR_DMAUDR2 (1 << 29)
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/**@}*/
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/* --- Function prototypes ------------------------------------------------- */
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/** @defgroup dac_channel_id DAC Channel Identifier
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* @{
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*/
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#define DAC_CHANNEL1 (1 << 0)
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#define DAC_CHANNEL2 (1 << 1)
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#define DAC_CHANNEL_BOTH (DAC_CHANNEL1 | DAC_CHANNEL2)
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/**@}*/
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/** DAC data size (8/12 bits), alignment (right/left) */
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enum dac_align {
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DAC_ALIGN_RIGHT8,
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DAC_ALIGN_RIGHT12,
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DAC_ALIGN_LEFT12,
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};
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/** DAC waveform generation options. */
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enum dac_wave {
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DAC_WAVE_DISABLE = 0,
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DAC_WAVE_NOISE = 1,
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DAC_WAVE_TRIANGLE = 2,
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DAC_WAVE_SAWTOOTH = 3,
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};
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BEGIN_DECLS
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void dac_enable(uint32_t dac, int channel);
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void dac_disable(uint32_t dac, int channel);
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void dac_buffer_enable(uint32_t dac, int channel);
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void dac_buffer_disable(uint32_t dac, int channel);
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void dac_dma_enable(uint32_t dac, int channel);
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void dac_dma_disable(uint32_t dac, int channel);
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void dac_trigger_enable(uint32_t dac, int channel);
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void dac_trigger_disable(uint32_t dac, int channel);
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void dac_set_trigger_source(uint32_t dac, uint32_t source);
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void dac_set_waveform_generation(uint32_t dac, enum dac_wave wave);
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void dac_disable_waveform_generation(uint32_t dac, int channel);
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void dac_set_waveform_characteristics(uint32_t dac, uint8_t mamp);
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void dac_load_data_buffer_single(uint32_t dac, uint16_t data,
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enum dac_align align, int channel);
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void dac_load_data_buffer_dual(uint32_t dac, uint16_t data1, uint16_t data2,
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enum dac_align align);
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void dac_software_trigger(uint32_t dac, int channel);
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END_DECLS
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#endif
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/** @cond */
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#else
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#warning "dac_common_all.h should not be included explicitly, only via dac.h"
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#endif
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/** @endcond */
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/**@}*/
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