107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/** @defgroup comp_defines COMP Defines
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*
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* @brief <b>libopencm3 Defined Constants and Types for the STM32F3xx
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* Comparator module</b>
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*
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* @ingroup STM32F3xx_defines
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*
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* @version 1.0.0
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*
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* @date 20 Jul 2018
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*
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*LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_COMP_H
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#define LIBOPENCM3_COMP_H
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/**@{*/
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#define COMP1 (COMP_BASE + 0x1C)
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#define COMP2 (COMP_BASE + 0x20)
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#define COMP3 (COMP_BASE + 0x24)
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#define COMP4 (COMP_BASE + 0x28)
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#define COMP5 (COMP_BASE + 0x2C)
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#define COMP6 (COMP_BASE + 0x30)
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#define COMP7 (COMP_BASE + 0x34)
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/* Comparator registers */
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/* Control and status register (COMPx_CSR) */
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#define COMP_CSR(comp_base) MMIO32((comp_base) + 0x00)
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#define COMP1_CSR COMP_CSR(COMP1)
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#define COMP2_CSR COMP_CSR(COMP2)
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#define COMP3_CSR COMP_CSR(COMP3)
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#define COMP4_CSR COMP_CSR(COMP4)
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#define COMP5_CSR COMP_CSR(COMP5)
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#define COMP6_CSR COMP_CSR(COMP6)
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#define COMP7_CSR COMP_CSR(COMP7)
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/* COMPx_CSR values */
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#define COMP_CSR_LOCK (0x1 << 31)
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#define COMP_CSR_OUT (0x1 << 30)
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/* individual blanking sources depends on COMP used */
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#define COMP_CSR_BLANKING_MASK (0x7)
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#define COMP_CSR_BLANKING_SHIFT (18)
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#define COMP_CSR_BLANKING_NONE (0x0)
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#define COMP_CSR_BLANKING(blanking) (((blanking) & COMP_CSR_BLANKING_MASK) << COMP_CSR_BLANKING_SHIFT)
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/* only on COMP1/3/5/7 */
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#define COMP_CSR_HYST_NONE (0x0)
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#define COMP_CSR_HYST_LOW (0x1)
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#define COMP_CSR_HYST_MEDIUM (0x2)
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#define COMP_CSR_HYST_HIGH (0x3)
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#define COMP_CSR_HYST_MASK (0x3)
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#define COMP_CSR_HYST_SHIFT (16)
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#define COMP_CSR_POL (0x1 << 15)
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/* individual value depends on COMP used */
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#define COMP_CSR_OUTSEL(outsel) (((outsel) & COMP_CSR_OUTSEL_MASK) << COMP_CSR_OUTSEL_SHIFT)
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#define COMP_CSR_OUTSEL_MASK (0xf)
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#define COMP_CSR_OUTSEL_SHIFT (10)
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/* only on COMP2/4/6 */
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#define COMP_CSR_WINMODE (0x1 << 9)
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/* not available on COMP1 */
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#define COMP_CSR_INPSEL (0x1 << 7)
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/* individual value depends on COMP used,
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also respects bit 3 (INMSEL[3]) where available */
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#define COMP_CSR_INMSEL(inmsel) ((((inmsel) & 0x7) << 4) | \
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((((inmsel) & 0x8) >> 3) << 22))
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#define COMP_CSR_INMSEL_MASK (0x7 << 4)
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#define COMP_CSR_MODE_HIGHSPEED (0x0)
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#define COMP_CSR_MODE_MEDIUMSPEED (0x1)
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#define COMP_CSR_MODE_LOWSPEED (0x2)
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#define COMP_CSR_MODE_ULTRALOWPOWER (0x3)
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#define COMP_CSR_MODE_MASK (0x3)
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#define COMP_CSR_MODE_SHIFT (2)
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/* only on COMP1 and COMP2 */
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#define COMP_CSR_INPDAC (0x1 << 1)
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#define COMP_CSR_EN (0x1 << 0)
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/**@}*/
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#endif
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