199 lines
6.9 KiB
C
199 lines
6.9 KiB
C
/** @defgroup adc_defines ADC Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F0xx Analog to Digital
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* Converter</b>
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*
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* @ingroup STM32F0xx_defines
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/stm32/common/adc_common_v2.h>
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#include <libopencm3/stm32/common/adc_common_v2_single.h>
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/*****************************************************************************/
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/* Module definitions */
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/*****************************************************************************/
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/** @defgroup adc_reg_base ADC register base addresses
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC ADC_BASE
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#define ADC1 ADC_BASE/* for API compatibility */
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/**@}*/
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/*****************************************************************************/
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/* Register definitions */
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/*****************************************************************************/
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#define ADC1_ISR ADC_ISR(ADC)
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#define ADC1_IER ADC_IER(ADC)
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#define ADC1_CR ADC_CR(ADC)
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#define ADC1_CFGR1 ADC_CFGR1(ADC)
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#define ADC1_CFGR2 ADC_CFGR2(ADC)
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#define ADC1_SMPR1 ADC_SMPR1(ADC)
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#define ADC_SMPR(adc) ADC_SMPR1(adc) /* Compatibility */
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#define ADC1_SMPR ADC_SMPR1(ADC) /* Compatibility */
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#define ADC1_TR1 ADC_TR1(ADC)
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#define ADC_TR(adc) ADC_TR1(adc) /* Compatibility */
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#define ADC1_TR ADC1_TR(ADC) /* Compatibility */
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#define ADC1_CHSELR ADC_CHSELR(ADC)
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#define ADC1_DR ADC_DR(ADC)
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#define ADC1_CCR ADC_CCR(ADC)
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* ADC_CFGR2 Values ---------------------------------------------------------*/
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#define ADC_CFGR2_CKMODE_SHIFT 30
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#define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT)
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#define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT)
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#define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT)
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#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT)
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/* ADC_SMPR Values ----------------------------------------------------------*/
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#define ADC_SMPR_SMP_SHIFT 0
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#define ADC_SMPR_SMP (7 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_001DOT5 (0 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_007DOT5 (1 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_013DOT5 (2 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_028DOT5 (3 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_041DOT5 (4 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_055DOT5 (5 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT)
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#define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT)
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/*****************************************************************************/
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/* API definitions */
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/*****************************************************************************/
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/** @defgroup adc_api_res ADC resolutions
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_RESOLUTION_12BIT ADC_CFGR1_RES_12_BIT
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#define ADC_RESOLUTION_10BIT ADC_CFGR1_RES_10_BIT
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#define ADC_RESOLUTION_8BIT ADC_CFGR1_RES_8_BIT
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#define ADC_RESOLUTION_6BIT ADC_CFGR1_RES_6_BIT
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/**@}*/
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/** @defgroup adc_api_smptime ADC sampling time
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_SMPTIME_001DOT5 ADC_SMPR_SMP_001DOT5
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#define ADC_SMPTIME_007DOT5 ADC_SMPR_SMP_007DOT5
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#define ADC_SMPTIME_013DOT5 ADC_SMPR_SMP_013DOT5
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#define ADC_SMPTIME_028DOT5 ADC_SMPR_SMP_028DOT5
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#define ADC_SMPTIME_041DOT5 ADC_SMPR_SMP_041DOT5
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#define ADC_SMPTIME_055DOT5 ADC_SMPR_SMP_055DOT5
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#define ADC_SMPTIME_071DOT5 ADC_SMPR_SMP_071DOT5
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#define ADC_SMPTIME_239DOT5 ADC_SMPR_SMP_239DOT5
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/**@}*/
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/** @defgroup adc_api_clksource ADC clock source
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_CK_ADC
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#define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2
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#define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4
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/**@}*/
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_CHANNEL_TEMP 16
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#define ADC_CHANNEL_VREF 17
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#define ADC_CHANNEL_VBAT 18
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/**@}*/
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/** @defgroup adc_api_opmode ADC Operation Modes
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* @ingroup adc_defines
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*
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*@{*/
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enum adc_opmode {
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ADC_MODE_SEQUENTIAL,
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ADC_MODE_SCAN,
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ADC_MODE_SCAN_INFINITE,
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};
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/**@}*/
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/*****************************************************************************/
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/* API Functions */
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/*****************************************************************************/
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BEGIN_DECLS
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/* Operation mode API */
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void adc_enable_discontinuous_mode(uint32_t adc);
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void adc_disable_discontinuous_mode(uint32_t adc);
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void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode);
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/* Trigger API */
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void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
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uint32_t polarity);
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void adc_disable_external_trigger_regular(uint32_t adc);
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/* Interrupt configuration */
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void adc_enable_watchdog_interrupt(uint32_t adc);
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void adc_disable_watchdog_interrupt(uint32_t adc);
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bool adc_get_watchdog_flag(uint32_t adc);
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void adc_clear_watchdog_flag(uint32_t adc);
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void adc_enable_eoc_sequence_interrupt(uint32_t adc);
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void adc_disable_eoc_sequence_interrupt(uint32_t adc);
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bool adc_get_eoc_sequence_flag(uint32_t adc);
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void adc_clear_eoc_sequence_flag(uint32_t adc);
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/* Basic configuration */
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void adc_set_clk_source(uint32_t adc, uint32_t source);
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void adc_enable_vbat_sensor(void);
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void adc_disable_vbat_sensor(void);
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void adc_calibrate_start(uint32_t adc)
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LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");
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void adc_calibrate_wait_finish(uint32_t adc)
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LIBOPENCM3_DEPRECATED("see adc_is_calibrating");
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/* Analog Watchdog */
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void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
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void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan);
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void adc_disable_analog_watchdog(uint32_t adc);
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void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
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void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
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END_DECLS
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#endif
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