401 lines
11 KiB
C
401 lines
11 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/stm32/exti.h>
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#define FALLING 0
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#define RISING 1
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u16 exti_direction = FALLING;
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void clock_setup(void)
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{
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rcc_clock_setup_in_hse_8mhz_out_72mhz();
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}
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void gpio_setup(void)
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{
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/* Enable GPIOC clock. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
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/* Set GPIO12 (in GPIO port C) to 'output push-pull'. */
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gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
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}
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void exti_setup(void)
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{
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/* Enable GPIOA clock. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
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/* Enable AFIO clock. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
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/* Enable EXTI0 interrupt. */
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nvic_enable_irq(NVIC_EXTI0_IRQ);
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/* Set GPIO0 (in GPIO port A) to 'input open-drain'. */
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gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO0);
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/* Configure the EXTI subsystem. */
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exti_select_source(EXTI0, GPIOA);
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exti_direction = FALLING;
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exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING);
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exti_enable_request(EXTI0);
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}
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void exti0_isr(void)
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{
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exti_reset_request(EXTI0);
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if (exti_direction == FALLING) {
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// gpio_toggle(GPIOA, GPIO12);
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exti_direction = RISING;
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exti_set_trigger(EXTI0, EXTI_TRIGGER_RISING);
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} else {
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// gpio_toggle(GPIOA, GPIO12);
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timer_generate_event(TIM1, TIM_EGR_COMG);
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exti_direction = FALLING;
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exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING);
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}
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}
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void tim_setup(void)
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{
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/* Enable TIM1 clock. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
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/* Enable GPIOA, GPIOB and Alternate Function clocks. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR,
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RCC_APB2ENR_IOPAEN |
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RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN);
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/*
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* Set TIM1 channel output pins to
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* 'output alternate function push-pull'.
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*/
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gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
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GPIO_TIM1_CH1 | GPIO_TIM1_CH2 | GPIO_TIM1_CH3);
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/*
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* Set TIM1 complementary channel output pins to
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* 'output alternate function push-pull'.
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*/
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gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
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GPIO_TIM1_CH1N | GPIO_TIM1_CH2N | GPIO_TIM1_CH3N);
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/* Enable TIM1 commutation interrupt. */
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nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ);
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/* Reset TIM1 peripheral. */
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timer_reset(TIM1);
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/* Timer global mode:
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* - No divider
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* - Alignment edge
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* - Direction up
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*/
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timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
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TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
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/* Reset prescaler value. */
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timer_set_prescaler(TIM1, 0);
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/* Reset repetition counter value. */
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timer_set_repetition_counter(TIM1, 0);
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/* Enable preload. */
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timer_enable_preload(TIM1);
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/* Continuous mode. */
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timer_continuous_mode(TIM1);
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/* Period (32kHz). */
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timer_set_period(TIM1, 72000000 / 32000);
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/* Configure break and deadtime. */
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timer_set_deadtime(TIM1, 10);
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timer_set_enabled_off_state_in_idle_mode(TIM1);
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timer_set_enabled_off_state_in_run_mode(TIM1);
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timer_disable_break(TIM1);
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timer_set_break_polarity_high(TIM1);
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timer_disable_break_automatic_output(TIM1);
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timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF);
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/* -- OC1 and OC1N configuration -- */
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC1);
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timer_disable_oc_output(TIM1, TIM_OC1N);
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/* Configure global mode of line 1. */
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timer_disable_oc_clear(TIM1, TIM_OC1);
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timer_enable_oc_preload(TIM1, TIM_OC1);
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timer_set_oc_slow_mode(TIM1, TIM_OC1);
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
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/* Configure OC1. */
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timer_set_oc_polarity_high(TIM1, TIM_OC1);
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timer_set_oc_idle_state_set(TIM1, TIM_OC1);
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/* Configure OC1N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC1N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC1N);
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/* Set the capture compare value for OC1. */
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timer_set_oc_value(TIM1, TIM_OC1, 100);
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC1);
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timer_enable_oc_output(TIM1, TIM_OC1N);
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/* -- OC2 and OC2N configuration -- */
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC2);
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timer_disable_oc_output(TIM1, TIM_OC2N);
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/* Configure global mode of line 2. */
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timer_disable_oc_clear(TIM1, TIM_OC2);
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timer_enable_oc_preload(TIM1, TIM_OC2);
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timer_set_oc_slow_mode(TIM1, TIM_OC2);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
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/* Configure OC2. */
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timer_set_oc_polarity_high(TIM1, TIM_OC2);
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timer_set_oc_idle_state_set(TIM1, TIM_OC2);
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/* Configure OC2N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC2N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC2N);
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/* Set the capture compare value for OC1. */
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timer_set_oc_value(TIM1, TIM_OC2, 100);
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC2);
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timer_enable_oc_output(TIM1, TIM_OC2N);
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/* -- OC3 and OC3N configuration -- */
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC3);
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timer_disable_oc_output(TIM1, TIM_OC3N);
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/* Configure global mode of line 3. */
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timer_disable_oc_clear(TIM1, TIM_OC3);
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timer_enable_oc_preload(TIM1, TIM_OC3);
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timer_set_oc_slow_mode(TIM1, TIM_OC3);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
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/* Configure OC3. */
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timer_set_oc_polarity_high(TIM1, TIM_OC3);
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timer_set_oc_idle_state_set(TIM1, TIM_OC3);
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/* Configure OC3N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC3N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC3N);
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/* Set the capture compare value for OC3. */
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timer_set_oc_value(TIM1, TIM_OC3, 100);
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC3);
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timer_enable_oc_output(TIM1, TIM_OC3N);
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/* ---- */
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/* ARR reload enable. */
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timer_enable_preload(TIM1);
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/*
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* Enable preload of complementary channel configurations and
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* update on COM event.
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*/
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timer_enable_preload_complementry_enable_bits(TIM1);
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/* Enable outputs in the break subsystem. */
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timer_enable_break_main_output(TIM1);
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/* Counter enable. */
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timer_enable_counter(TIM1);
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/* Enable commutation interrupt. */
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timer_enable_irq(TIM1, TIM_DIER_COMIE);
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}
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void tim1_trg_com_isr(void)
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{
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static int step = 0;
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/* Clear the COM trigger interrupt flag. */
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timer_clear_flag(TIM1, TIM_SR_COMIF);
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/*
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* A simplified and inefficient implementation of PWM On
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* scheme. Look at the implementation in Open-BLDC on
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* http://open-bldc.org for the proper implementation. This
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* one only serves as an example.
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*
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* Table of the PWM scheme zone configurations when driving:
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* @verbatim
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* | 1| 2| 3| 4| 5| 6|
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* -+--+--+--+--+--+--+
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* A|p+|++| |p-|--| |
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* -+--+--+--+--+--+--+
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* B| |p-|--| |p+|++|
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* -+--+--+--+--+--+--+
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* C|--| |p+|++| |p-|
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* -+--+--+--+--+--+--+
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* | | | | | | '- 360 Deg
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* | | | | | '---- 300 Deg
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* | | | | '------- 240 Deg
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* | | | '---------- 180 Deg
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* | | '------------- 120 Deg
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* | '---------------- 60 Deg
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* '------------------- 0 Deg
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*
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* Legend:
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* p+: PWM on the high side
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* p-: PWM on the low side
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* --: Low side on
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* ++: High side on
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* : Floating/NC
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* @endverbatim
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*/
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switch (step) {
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case 0: /* A PWM HIGH, B OFF, C LOW */
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_LOW);
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timer_enable_oc_output(TIM1, TIM_OC1);
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timer_disable_oc_output(TIM1, TIM_OC1N);
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timer_disable_oc_output(TIM1, TIM_OC2);
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timer_disable_oc_output(TIM1, TIM_OC2N);
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timer_enable_oc_output(TIM1, TIM_OC3);
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timer_enable_oc_output(TIM1, TIM_OC3N);
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step++;
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break;
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case 1: /* A HIGH, B PWM LOW, C OFF */
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN);
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timer_enable_oc_output(TIM1, TIM_OC1);
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timer_enable_oc_output(TIM1, TIM_OC1N);
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timer_disable_oc_output(TIM1, TIM_OC2);
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timer_enable_oc_output(TIM1, TIM_OC2N);
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timer_disable_oc_output(TIM1, TIM_OC3);
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timer_disable_oc_output(TIM1, TIM_OC3N);
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step++;
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break;
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case 2: /* A OFF, B LOW, C PWM HIGH */
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_LOW);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
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timer_disable_oc_output(TIM1, TIM_OC1);
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timer_disable_oc_output(TIM1, TIM_OC1N);
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timer_enable_oc_output(TIM1, TIM_OC2);
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timer_enable_oc_output(TIM1, TIM_OC2N);
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timer_enable_oc_output(TIM1, TIM_OC3);
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timer_disable_oc_output(TIM1, TIM_OC3N);
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step++;
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break;
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case 3: /* A PWM LOW, B OFF, C HIGH */
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH);
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timer_disable_oc_output(TIM1, TIM_OC1);
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timer_enable_oc_output(TIM1, TIM_OC1N);
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timer_disable_oc_output(TIM1, TIM_OC2);
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timer_disable_oc_output(TIM1, TIM_OC2N);
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timer_enable_oc_output(TIM1, TIM_OC3);
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timer_enable_oc_output(TIM1, TIM_OC3N);
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step++;
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break;
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case 4: /* A LOW, B PWM HIGH, C OFF */
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_LOW);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN);
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timer_enable_oc_output(TIM1, TIM_OC1);
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timer_enable_oc_output(TIM1, TIM_OC1N);
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timer_enable_oc_output(TIM1, TIM_OC2);
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timer_disable_oc_output(TIM1, TIM_OC2N);
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timer_disable_oc_output(TIM1, TIM_OC3);
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timer_disable_oc_output(TIM1, TIM_OC3N);
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step++;
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break;
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case 5: /* A OFF, B HIGH, C PWM LOW */
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
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timer_disable_oc_output(TIM1, TIM_OC1);
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timer_disable_oc_output(TIM1, TIM_OC1N);
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timer_enable_oc_output(TIM1, TIM_OC2);
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timer_enable_oc_output(TIM1, TIM_OC2N);
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timer_disable_oc_output(TIM1, TIM_OC3);
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timer_enable_oc_output(TIM1, TIM_OC3N);
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step = 0;
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break;
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}
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gpio_toggle(GPIOC, GPIO12);
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}
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int main(void)
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{
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clock_setup();
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gpio_setup();
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tim_setup();
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exti_setup();
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while (1)
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__asm("nop");
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return 0;
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}
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