260 lines
8.5 KiB
C
260 lines
8.5 KiB
C
/** @addtogroup adc_defines
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@author @htmlonly © @endhtmlonly 2015 Karl Palsson <karlp@tweak.net.au>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
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The order of header inclusion is important. adc.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_ADC_H
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/** @endcond */
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#ifndef LIBOPENCM3_ADC_COMMON_V2_H
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#define LIBOPENCM3_ADC_COMMON_V2_H
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/* ----- ADC registers -----------------------------------------------------*/
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/** ADC interrupt and status register */
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#define ADC_ISR(adc) MMIO32((adc) + 0x00)
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/** Interrupt Enable Register */
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#define ADC_IER(adc) MMIO32((adc) + 0x04)
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/** Control Register */
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#define ADC_CR(adc) MMIO32((adc) + 0x08)
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/** Configuration Register 1 */
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#define ADC_CFGR1(adc) MMIO32((adc) + 0x0C)
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/** Configuration Register 2 */
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#define ADC_CFGR2(adc) MMIO32((adc) + 0x10)
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/** Sample Time Register 1 */
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#define ADC_SMPR1(adc) MMIO32((adc) + 0x14)
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/** Watchdog Threshold Register 1*/
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#define ADC_TR1(adc) MMIO32((adc) + 0x20)
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/** Regular Data Register */
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#define ADC_DR(adc) MMIO32((adc) + 0x40)
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/* CALFACT for all but f0 :(*/
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/** Common Configuration register */
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#define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8)
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/* --- Register values -------------------------------------------------------*/
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/* ADC_ISR Values -----------------------------------------------------------*/
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/** @defgroup adc_isr ISR ADC interrupt status register
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@{*/
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/** AWD1: Analog watchdog 1 flag */
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#define ADC_ISR_AWD1 (1 << 7)
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/** OVR: Overrun flag */
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#define ADC_ISR_OVR (1 << 4)
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/** EOS: End of sequence conversions flag */
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#define ADC_ISR_EOS (1 << 3) // FIXME - move to single/multi here.
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#define ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */
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/** EOS: End of regular conversion flag */
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#define ADC_ISR_EOC (1 << 2)
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/** EOSMP: End of sampling flag */
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#define ADC_ISR_EOSMP (1 << 1)
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/** ADRDY: Ready flag */
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#define ADC_ISR_ADRDY (1 << 0)
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/**@}*/
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/* ADC_IER Values -----------------------------------------------------------*/
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/** @defgroup adc_ier IER ADC interrupt enable register
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@{*/
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/** AWD1IE: Analog watchdog 1 interrupt enable */
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#define ADC_IER_AWD1IE (1 << 7)
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/** OVRIE: Overrun interrupt enable */
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#define ADC_IER_OVRIE (1 << 4)
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/** EOSIE: End of regular sequence of conversions interrupt enable */
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#define ADC_IER_EOSIE (1 << 3)
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#define ADC_IER_EOSEQIE ADC_IER_EOSIE /* TODO - keep only one? */
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/** EOCIE: End of regular conversion interrupt enable */
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#define ADC_IER_EOCIE (1 << 2)
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/** EOSMPIE: End of sampling flag interrupt enable for regular conversions */
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#define ADC_IER_EOSMPIE (1 << 1)
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/** ADRDYIE: ADC ready interrupt enable */
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#define ADC_IER_ADRDYIE (1 << 0)
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/**@}*/
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/* ADC_CR Values -----------------------------------------------------------*/
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/** @defgroup adc_cr CR ADC control register
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@{*/
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/** ADCAL: ADC calibration */
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#define ADC_CR_ADCAL (1 << 31)
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/** ADSTP: ADC stop of regular conversion command */
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#define ADC_CR_ADSTP (1 << 4)
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/** ADSTART: ADC start of regular conversion */
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#define ADC_CR_ADSTART (1 << 2)
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/** ADDIS: ADC disable command */
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#define ADC_CR_ADDIS (1 << 1)
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/** ADEN: ADC enable control */
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#define ADC_CR_ADEN (1 << 0)
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/**@}*/
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/* ADC_CFGR1 Values -----------------------------------------------------------*/
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/** @defgroup adc_cfgr1 CFGR1 ADC configuration register 1
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@{*/
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#define ADC_CFGR1_AWD1CH_SHIFT 26
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#define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)
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/** AWD1CH: Analog watchdog 1 channel selection */
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#define ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT)
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/** AWD1EN: Analog watchdog 1 enable on regular channels */
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#define ADC_CFGR1_AWD1EN (1 << 23)
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/** AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */
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#define ADC_CFGR1_AWD1SGL (1 << 22)
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/** DISCEN: Discontinuous mode for regular channels */
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#define ADC_CFGR1_DISCEN (1 << 16)
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/** AUTDLY: Delayed conversion mode */
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#define ADC_CFGR1_AUTDLY (1 << 14)
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/** CONT: Single / continuous conversion mode for regular conversions */
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#define ADC_CFGR1_CONT (1 << 13)
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/** OVRMOD: Overrun Mode */
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#define ADC_CFGR1_OVRMOD (1 << 12)
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#define ADC_CFGR1_EXTEN_MASK (0x3 << 10)
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/** @defgroup adc_cfgr1_exten EXTEN: External trigger enable and polarity selection for regular channels
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@{*/
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#define ADC_CFGR1_EXTEN_DISABLED (0x0 << 10)
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#define ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10)
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#define ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10)
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#define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10)
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/**@}*/
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/** ALIGN: Data alignment */
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#define ADC_CFGR1_ALIGN (1 << 5)
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#define ADC_CFGR1_RES_MASK (0x3 << 3)
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/** @defgroup adc_cfgr1_res RES: Data resolution
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@{*/
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#define ADC_CFGR1_RES_12_BIT (0x0 << 3)
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#define ADC_CFGR1_RES_10_BIT (0x1 << 3)
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#define ADC_CFGR1_RES_8_BIT (0x2 << 3)
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#define ADC_CFGR1_RES_6_BIT (0x3 << 3)
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/**@}*/
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/** DMACFG: Direct memory access configuration */
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#define ADC_CFGR1_DMACFG (1 << 1)
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/** DMAEN: Direct memory access enable */
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#define ADC_CFGR1_DMAEN (1 << 0)
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/**@}*/
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/* ADC_SMPR Values -----------------------------------------------------------*/
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/** @defgroup adc_smpr SMPR ADC sample time register
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@{*/
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/**@}*/
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/* ADC_CFGR2 Values -----------------------------------------------------------*/
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/** @defgroup adc_cfgr2 CFGR2 ADC configuration register 2
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@{*/
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/**@}*/
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/* ADC_TR1 Values ------------------------------------------------------------*/
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/** @defgroup adc_tr1 TR1 ADC watchdog threshold register 1
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@{*/
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#define ADC_TR1_LT_SHIFT 0
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#define ADC_TR1_LT_MASK 0xFFF
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#define ADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT)
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/** TR1_LT: analog watchdog 1 threshold low */
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#define ADC_TR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT)
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#define ADC_TR1_HT_SHIFT 16
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#define ADC_TR1_HT_MASK 0xFFF
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#define ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT)
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/** TR1_HT: analog watchdog 1 threshold high */
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#define ADC_TR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT)
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/**@}*/
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/* ADC_CCR Values -----------------------------------------------------------*/
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/** @defgroup adc_ccr CCR ADC common configuration register
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@{*/
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/** VBATEN: Enable VBAT Channel */
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#define ADC_CCR_VBATEN (1 << 24)
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/** TSEN: Enable Temperature Sensor */
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#define ADC_CCR_TSEN (1 << 23)
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/** VREFEN: Enable internal Voltage Reference */
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#define ADC_CCR_VREFEN (1 << 22)
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/**@}*/
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void adc_power_on_async(uint32_t adc);
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void adc_power_on(uint32_t adc);
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bool adc_is_power_on(uint32_t adc);
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void adc_power_off_async(uint32_t adc);
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void adc_power_off(uint32_t adc);
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bool adc_is_power_off(uint32_t adc);
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void adc_calibrate_async(uint32_t adc);
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bool adc_is_calibrating(uint32_t adc);
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void adc_calibrate(uint32_t adc);
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void adc_set_continuous_conversion_mode(uint32_t adc);
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void adc_set_single_conversion_mode(uint32_t adc);
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void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
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void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
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void adc_enable_temperature_sensor(void);
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void adc_disable_temperature_sensor(void);
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void adc_enable_vrefint(void);
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void adc_disable_vrefint(void);
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void adc_set_resolution(uint32_t adc, uint16_t resolution);
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void adc_set_left_aligned(uint32_t adc);
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void adc_set_right_aligned(uint32_t adc);
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void adc_enable_dma(uint32_t adc);
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void adc_disable_dma(uint32_t adc);
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bool adc_eoc(uint32_t adc);
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bool adc_eos(uint32_t adc);
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void adc_enable_eoc_interrupt(uint32_t adc);
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void adc_disable_eoc_interrupt(uint32_t adc);
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void adc_enable_overrun_interrupt(uint32_t adc);
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void adc_disable_overrun_interrupt(uint32_t adc);
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bool adc_get_overrun_flag(uint32_t adc);
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void adc_clear_overrun_flag(uint32_t adc);
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uint32_t adc_read_regular(uint32_t adc);
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void adc_start_conversion_regular(uint32_t adc);
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void adc_enable_dma_circular_mode(uint32_t adc);
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void adc_disable_dma_circular_mode(uint32_t adc);
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END_DECLS
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#endif
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/** @cond */
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#endif
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/** @endcond */
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/**@}*/
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