622 lines
15 KiB
C
622 lines
15 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/efm32/dma.h>
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#define CHANNEL_SUPPORT_LOOP(ch) (((ch) == DMA_CH0) || ((ch) == DMA_CH1))
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/**
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* Enable DMA with privileged access
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* @see dma_enable_with_unprivileged_access()
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*/
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void dma_enable_with_privileged_access(void)
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{
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DMA_CONFIG = DMA_CONFIG_EN | DMA_CONFIG_CHPROT;
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}
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/**
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* Enable DMA with un-privileged access
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* @see dma_enable_with_privileged_access()
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*/
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void dma_enable_with_unprivileged_access(void)
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{
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DMA_CONFIG = DMA_CONFIG_EN;
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}
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/**
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* same as @a dma_enable_with_unprivileged_access()
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* @see dma_enable_with_unprivileged_access()
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*/
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void dma_enable(void)
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{
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dma_enable_with_unprivileged_access();
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}
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/**
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* Disable DMA
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*/
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void dma_disable(void)
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{
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DMA_CONFIG = 0;
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}
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/**
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* Set channel's descriptor address
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* @param[in] desc_base Address of channel's descriptor address
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* @note @a desc_base 8LSB's should be 0x00
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*/
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void dma_set_desc_address(uint32_t desc_base)
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{
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if (desc_base & 0xFF) {
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return;
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}
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DMA_CTRLBASE = desc_base;
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}
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/**
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* Get channel wait on request status flag
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* @retval true if flag is set
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* @retval false if flag is not set
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*/
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bool dma_get_wait_on_request_flag(enum dma_ch ch)
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{
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uint32_t mask = DMA_CHWAITSTATUS_CHxWAITSTATUS(ch);
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return (DMA_CHWAITSTATUS & mask) != 0;
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}
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/**
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* Generate a software request on channel
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_generate_software_request(enum dma_ch ch)
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{
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DMA_CHSWREQ = DMA_CHSWREQ_CHxSWREQ(ch);
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}
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/**
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* Enable channel burst only
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_burst_only(enum dma_ch ch)
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{
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DMA_CHUSEBURSTS = DMA_CHUSEBURSTS_CHxSUSEBURSTS(ch);
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}
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/**
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* Enable channel single and burst
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_single_and_burst(enum dma_ch ch)
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{
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DMA_CHUSEBURSTC = DMA_CHUSEBURSTC_CHxSUSEBURSTC(ch);
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}
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/**
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* Enable channel peripherial request
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_periph_request(enum dma_ch ch)
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{
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DMA_CHREQMASKC = DMA_CHREQMASKC_CHxSREQMASKC(ch);
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}
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/**
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* Disable channel peripherial request
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_disable_periph_request(enum dma_ch ch)
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{
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DMA_CHREQMASKS = DMA_CHREQMASKS_CHxSREQMASKS(ch);
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}
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/**
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* Enable channel
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_channel(enum dma_ch ch)
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{
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DMA_CHENS = DMA_CHENS_CHxSENS(ch);
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}
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/**
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* Disable channel
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_disable_channel(enum dma_ch ch)
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{
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DMA_CHENC = DMA_CHENC_CHxSENC(ch);
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}
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/**
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* Disable channel alternate structure
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_disable_alternate_structure(enum dma_ch ch)
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{
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DMA_CHALTC = DMA_CHALTC_CHxSALTC(ch);
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}
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/**
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* Enable channel alternate structure
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_alternate_structure(enum dma_ch ch)
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{
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DMA_CHALTS = DMA_CHALTS_CHxSALTS(ch);
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}
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/**
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* Enable channel high priority
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_priority(enum dma_ch ch)
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{
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DMA_CHPRIS = DMA_CHPRIS_CHxSPRIC(ch);
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}
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/**
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* Disable channel high priority
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_disable_priority(enum dma_ch ch)
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{
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DMA_CHPRIC = DMA_CHPRIC_CHxSPRIC(ch);
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}
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/**
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* Get bus error flag
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* @retval true if flag is set
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* @retval false if flag is not set
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*/
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bool dma_get_bus_error_flag(void)
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{
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return (DMA_ERRORC & DMA_ERRORC_ERRORC) != 0;
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}
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/**
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* Clear bus error flag
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*/
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void dma_clear_bus_error_flag(void)
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{
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DMA_ERRORC = DMA_ERRORC_ERRORC;
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}
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/**
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* Get channel request flag
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* @param[in] ch Channel (use DMA_CHx)
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* @retval true if flag is set
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* @retval false if flag is not set
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*/
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bool dma_get_request_flag(enum dma_ch ch)
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{
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uint32_t mask = DMA_CHREQSTATUS_CHxSREQSTATUS(ch);
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return (DMA_CHREQSTATUS & mask) != 0;
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}
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/**
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* Get bus error interrupt flag
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* @retval true if flag is set
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* @retval false if flag is not set
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*/
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bool dma_get_bus_error_interrupt_flag(void)
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{
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return (DMA_IF & DMA_IF_ERR) != 0;
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}
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/**
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* Get channel done interrupt flag
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* @param[in] ch Channel (use DMA_CHx)
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* @retval true if flag is set
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* @retval false if flag is not set
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*
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*/
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bool dma_get_done_interrupt_flag(enum dma_ch ch)
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{
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return (DMA_IF & DMA_IF_CHxDONE(ch)) != 0;
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}
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/**
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* Set bus error interrupt flag
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*/
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void dma_set_bus_error_interrupt_flag(void)
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{
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DMA_IFS = DMA_IFS_ERR;
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}
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/**
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* Set channel done interrupt flag
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_set_done_interrupt_flag(enum dma_ch ch)
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{
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DMA_IFS = DMA_IFS_CHxDONE(ch);
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}
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/**
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* Clear bus error interrupt flag
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*/
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void dma_clear_bus_error_interrupt_flag(void)
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{
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DMA_IFC = DMA_IFC_ERR;
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}
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/**
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* Clear channel done interrupt flag
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_clear_done_interrupt_flag(enum dma_ch ch)
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{
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DMA_IFC = DMA_IFC_CHxDONE(ch);
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}
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/**
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* Enable bus error interrupt
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*/
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void dma_enable_bus_error_interrupt(void)
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{
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DMA_IEN |= DMA_IEN_ERR;
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}
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/**
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* Disable bus error interrupt
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*/
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void dma_disable_bus_error_interrupt(void)
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{
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DMA_IEN &= ~DMA_IEN_ERR;
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}
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/**
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* Enable channel done interrupt
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_done_interrupt(enum dma_ch ch)
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{
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DMA_IEN |= DMA_IEN_CHxDONE(ch);
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}
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/**
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* Disable channel done interrupt
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_disable_done_interrupt(enum dma_ch ch)
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{
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DMA_IEN &= ~DMA_IEN_CHxDONE(ch);
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}
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/**
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* Set channel source
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] source Source (use DMA_CH_CTRL_SOURCESEL_*)
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*/
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void dma_set_source(enum dma_ch ch, uint32_t source)
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{
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DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SOURCESEL_MASK)
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| source;
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}
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/**
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* Set channel source signal
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] signal Signal (use DMA_CH_CTRL_SIGSEL_*)
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*/
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void dma_set_signal(enum dma_ch ch, uint32_t signal)
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{
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DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SIGSEL_MASK)
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| signal;
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}
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/**
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* Reset channel
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_channel_reset(enum dma_ch ch)
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{
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/* Disable channel */
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DMA_CHENC = DMA_CHENC_CHxSENC(ch);
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/* reset channel alternate desc */
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DMA_CHALTC = DMA_CHALTC_CHxSALTC(ch);
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/* reset channel priority */
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DMA_CHPRIC = DMA_CHPRIC_CHxSPRIC(ch);
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/* clear channel interrupt */
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DMA_IFC = DMA_IFC_CHxDONE(ch);
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/* disable loop */
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if (CHANNEL_SUPPORT_LOOP(ch)) {
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DMA_LOOPx(ch) = 0;
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}
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/* reset signal {source, select} */
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DMA_CHx_CTRL(ch) = 0;
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}
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/**
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* Set channel loop width to ( @a count + 1)
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] count Count
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* @note @a count is expected to be equal to (n_minus_1 + 1)
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*/
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void dma_set_loop_count(enum dma_ch ch, uint16_t count)
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{
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if (!CHANNEL_SUPPORT_LOOP(ch)) {
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return;
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}
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DMA_LOOPx(ch) = (DMA_LOOPx(ch) & ~DMA_LOOP_WIDTH_MASK)
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| DMA_LOOP_WIDTH(count - 1);
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}
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/**
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* Enable channel loop
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_enable_loop(enum dma_ch ch)
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{
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if (!CHANNEL_SUPPORT_LOOP(ch)) {
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return;
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}
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DMA_LOOPx(ch) |= DMA_LOOP_EN;
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}
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/**
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* Disable channel loop
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_disable_loop(enum dma_ch ch)
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{
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if (!CHANNEL_SUPPORT_LOOP(ch)) {
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return;
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}
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DMA_LOOPx(ch) &= ~DMA_LOOP_EN;
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}
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/**
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* Set desination size
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] size Size (use DMA_MEM_*)
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*/
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void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch,
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enum dma_mem size)
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{
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uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
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cfg &= ~DMA_DESC_CH_CFG_DEST_SIZE_MASK;
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cfg |= DMA_DESC_CH_CFG_DEST_SIZE(size);
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DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
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}
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/**
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* Set destination increment
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] inc Increment (use DMA_MEM_*)
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*/
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void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch,
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enum dma_mem inc)
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{
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uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
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cfg &= ~DMA_DESC_CH_CFG_DEST_INC_MASK;
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cfg |= DMA_DESC_CH_CFG_DEST_INC(inc);
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DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
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}
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/**
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* Set source size
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] size Size (use DMA_MEM_*)
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*/
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void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch,
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enum dma_mem size)
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{
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uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
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cfg &= ~DMA_DESC_CH_CFG_SRC_SIZE_MASK;
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cfg |= DMA_DESC_CH_CFG_SRC_SIZE(size);
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DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
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}
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/**
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* Set source increment
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] inc Increment (use DMA_MEM_*)
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*/
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void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
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{
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uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
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cfg &= ~DMA_DESC_CH_CFG_SRC_INC_MASK;
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cfg |= DMA_DESC_CH_CFG_SRC_INC(inc);
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DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
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}
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/**
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* Set R Power
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] r_power R Power (Use DMA_R_POWER_*)
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*/
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void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch,
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enum dma_r_power r_power)
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{
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uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
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cfg &= ~DMA_DESC_CH_CFG_R_POWER_MASK;
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cfg |= DMA_DESC_CH_CFG_R_POWER(r_power);
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DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
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}
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/**
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* Enable next useburst
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch)
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{
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DMA_DESC_CHx_CFG(desc_base, ch) &= ~DMA_DESC_CH_CFG_NEXT_USEBURST;
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}
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/**
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* Disable next useburst
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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*/
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void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch)
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{
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DMA_DESC_CHx_CFG(desc_base, ch) |= DMA_DESC_CH_CFG_NEXT_USEBURST;
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}
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/**
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* Set number (count) of transfer to be performed
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] count Count
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*/
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void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count)
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{
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uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
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cfg &= ~DMA_DESC_CH_CFG_N_MINUS_1_MASK;
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cfg |= DMA_DESC_CH_CFG_N_MINUS_1(count - 1);
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DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
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}
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/**
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* Store user data field in channel descriptor
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @param[in] user_data User data
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*/
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void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch,
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uint32_t user_data)
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{
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DMA_DESC_CHx_USER_DATA(desc_base, ch) = user_data;
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}
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/**
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* Extract user data field from channel descriptor
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* @param[in] desc_base start of memory location that contain channel
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* descriptor
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* @param[in] ch Channel (use DMA_CHx)
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* @return user data
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*/
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uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch)
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{
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return DMA_DESC_CHx_USER_DATA(desc_base, ch);
|
|
}
|
|
|
|
/**
|
|
* Calculate end from start address.
|
|
*
|
|
* @details
|
|
* See "8.4.3.4 Address calculation" p68, EFM32LG-RM "d0183_Rev1.10"
|
|
*
|
|
* @param[in] start address to start of memory
|
|
* @param[in] inc Increment (use DMA_MEM_*)
|
|
* @param[in] n_minus_1 the number of transfers minus 1 (ie count - 1)
|
|
* @return the calculate end address
|
|
* @note can be used to calculate {source, destination} end address
|
|
*/
|
|
static inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc,
|
|
uint16_t n_minus_1)
|
|
{
|
|
switch (inc) {
|
|
case DMA_MEM_BYTE:
|
|
return start + n_minus_1;
|
|
case DMA_MEM_HALF_WORD:
|
|
return start + (n_minus_1 << 1);
|
|
case DMA_MEM_WORD:
|
|
return start + (n_minus_1 << 2);
|
|
case DMA_MEM_NONE:
|
|
return start;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Assign Source address to DMA Channel
|
|
* @param[in] desc_base start of memory location that contain channel
|
|
* descriptor
|
|
* @param[in] ch Channel (use DMA_CHx)
|
|
* @param[in] src_start Source data start address
|
|
* @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc()
|
|
* set value to calculate the src data end address from @a src_start
|
|
* @note dma_desc_set_count() should be called first.
|
|
* @note dma_desc_set_src_inc() should be called first.
|
|
*/
|
|
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch,
|
|
uint32_t src_start)
|
|
{
|
|
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
|
uint8_t inc = (cfg & DMA_DESC_CH_CFG_SRC_INC_MASK)
|
|
>> DMA_DESC_CH_CFG_SRC_INC_SHIFT;
|
|
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK)
|
|
>> DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
|
|
uint32_t src_end = dma_calc_end_from_start(src_start, inc, n_minus_1);
|
|
DMA_DESC_CHx_SRC_DATA_END_PTR(desc_base, ch) = src_end;
|
|
}
|
|
|
|
/**
|
|
* Assign Destination address to DMA Channel
|
|
* @param[in] desc_base start of memory location that contain channel
|
|
* descriptor
|
|
* @param[in] ch Channel (use DMA_CHx)
|
|
* @param[in] dest_start Destination data start address
|
|
* @param[in] this function use dma_desc_set_count() and
|
|
* dma_desc_set_dest_inc() set value to calculate the dest data end
|
|
* address from @a dest_start
|
|
* @note dma_desc_set_count() should be called first.
|
|
* @note dma_desc_set_dest_inc() should be called first.
|
|
*/
|
|
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch,
|
|
uint32_t dest_start)
|
|
{
|
|
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
|
uint8_t inc = (cfg & DMA_DESC_CH_CFG_DEST_INC_MASK)
|
|
>> DMA_DESC_CH_CFG_DEST_INC_SHIFT;
|
|
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK)
|
|
>> DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
|
|
uint32_t dest_end = dma_calc_end_from_start(dest_start, inc,
|
|
n_minus_1);
|
|
DMA_DESC_CHx_DEST_DATA_END_PTR(desc_base, ch) = dest_end;
|
|
}
|
|
|
|
/**
|
|
* Set the channel mode ("Cycle control")
|
|
* @param[in] desc_base start of memory location that contain channel
|
|
* descriptor
|
|
* @param[in] ch Channel (use DMA_CHx)
|
|
* @param[in] mode Mode (use DMA_MODE_*)
|
|
*/
|
|
void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode)
|
|
{
|
|
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
|
cfg &= ~DMA_DESC_CH_CFG_CYCLE_CTRL_MASK;
|
|
cfg |= DMA_DESC_CH_CFG_CYCLE_CTRL(mode);
|
|
DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
|
|
}
|