938 lines
22 KiB
YAML
938 lines
22 KiB
YAML
!!omap
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- CGU_FREQ_MON:
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fields: !!omap
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- RCNT:
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access: rw
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description: 9-bit reference clock-counter value
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lsb: 0
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reset_value: '0'
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width: 9
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- FCNT:
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access: r
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description: 14-bit selected clock-counter value
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lsb: 9
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reset_value: '0'
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width: 14
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- MEAS:
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access: rw
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description: Measure frequency
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lsb: 23
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock-source selection for the clock to be measured
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lsb: 24
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reset_value: '0'
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width: 5
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- CGU_XTAL_OSC_CTRL:
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fields: !!omap
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- ENABLE:
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access: rw
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description: Oscillator-pad enable
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lsb: 0
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reset_value: '1'
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width: 1
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- BYPASS:
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access: rw
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description: Configure crystal operation or external-clock input pin XTAL1
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lsb: 1
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reset_value: '0'
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width: 1
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- HF:
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access: rw
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description: Select frequency range
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lsb: 2
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reset_value: '1'
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width: 1
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- CGU_PLL0USB_STAT:
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fields: !!omap
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- LOCK:
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access: r
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description: PLL0 lock indicator
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lsb: 0
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reset_value: '0'
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width: 1
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- FR:
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access: r
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description: PLL0 free running indicator
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lsb: 1
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reset_value: '0'
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width: 1
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- CGU_PLL0USB_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: PLL0 power down
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lsb: 0
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reset_value: '1'
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width: 1
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- BYPASS:
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access: rw
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description: Input clock bypass control
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lsb: 1
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reset_value: '1'
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width: 1
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- DIRECTI:
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access: rw
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description: PLL0 direct input
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lsb: 2
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reset_value: '0'
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width: 1
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- DIRECTO:
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access: rw
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description: PLL0 direct output
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lsb: 3
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reset_value: '0'
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width: 1
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- CLKEN:
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access: rw
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description: PLL0 clock enable
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lsb: 4
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reset_value: '0'
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width: 1
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- FRM:
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access: rw
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description: Free running mode
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lsb: 6
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reset_value: '0'
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width: 1
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_PLL0USB_MDIV:
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fields: !!omap
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- MDEC:
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access: rw
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description: Decoded M-divider coefficient value
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lsb: 0
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reset_value: '0x5B6A'
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width: 17
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- SELP:
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access: rw
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description: Bandwidth select P value
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lsb: 17
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reset_value: '0x1C'
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width: 5
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- SELI:
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access: rw
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description: Bandwidth select I value
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lsb: 22
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reset_value: '0x17'
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width: 6
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- SELR:
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access: rw
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description: Bandwidth select R value
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lsb: 28
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reset_value: '0x0'
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width: 4
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- CGU_PLL0USB_NP_DIV:
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fields: !!omap
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- PDEC:
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access: rw
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description: Decoded P-divider coefficient value
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lsb: 0
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reset_value: '0x02'
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width: 7
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- NDEC:
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access: rw
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description: Decoded N-divider coefficient value
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lsb: 12
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reset_value: '0xB1'
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width: 10
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- CGU_PLL0AUDIO_STAT:
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fields: !!omap
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- LOCK:
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access: r
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description: PLL0 lock indicator
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lsb: 0
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reset_value: '0'
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width: 1
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- FR:
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access: r
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description: PLL0 free running indicator
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lsb: 1
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reset_value: '0'
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width: 1
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- CGU_PLL0AUDIO_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: PLL0 power down
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lsb: 0
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reset_value: '1'
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width: 1
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- BYPASS:
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access: rw
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description: Input clock bypass control
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lsb: 1
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reset_value: '1'
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width: 1
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- DIRECTI:
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access: rw
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description: PLL0 direct input
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lsb: 2
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reset_value: '0'
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width: 1
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- DIRECTO:
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access: rw
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description: PLL0 direct output
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lsb: 3
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reset_value: '0'
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width: 1
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- CLKEN:
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access: rw
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description: PLL0 clock enable
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lsb: 4
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reset_value: '0'
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width: 1
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- FRM:
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access: rw
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description: Free running mode
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lsb: 6
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reset_value: '0'
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width: 1
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- PLLFRACT_REQ:
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access: rw
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description: Fractional PLL word write request
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lsb: 12
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reset_value: '0'
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width: 1
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- SEL_EXT:
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access: rw
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description: Select fractional divider
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lsb: 13
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reset_value: '0'
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width: 1
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- MOD_PD:
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access: rw
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description: Sigma-Delta modulator power-down
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lsb: 14
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reset_value: '1'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_PLL0AUDIO_MDIV:
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fields: !!omap
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- MDEC:
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access: rw
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description: Decoded M-divider coefficient value
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lsb: 0
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reset_value: '0x5B6A'
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width: 17
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- CGU_PLL0AUDIO_NP_DIV:
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fields: !!omap
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- PDEC:
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access: rw
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description: Decoded P-divider coefficient value
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lsb: 0
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reset_value: '0x02'
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width: 7
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- NDEC:
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access: rw
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description: Decoded N-divider coefficient value
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lsb: 12
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reset_value: '0xB1'
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width: 10
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- CGU_PLLAUDIO_FRAC:
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fields: !!omap
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- PLLFRACT_CTRL:
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access: rw
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description: PLL fractional divider control word
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lsb: 0
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reset_value: '0x00'
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width: 22
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- CGU_PLL1_STAT:
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fields: !!omap
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- LOCK:
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access: r
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description: PLL1 lock indicator
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lsb: 0
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reset_value: '0'
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width: 1
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- CGU_PLL1_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: PLL1 power down
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lsb: 0
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reset_value: '1'
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width: 1
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- BYPASS:
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access: rw
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description: Input clock bypass control
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lsb: 1
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reset_value: '1'
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width: 1
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- FBSEL:
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access: rw
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description: PLL feedback select
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lsb: 6
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reset_value: '0'
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width: 1
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- DIRECT:
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access: rw
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description: PLL direct CCO output
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lsb: 7
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reset_value: '0'
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width: 1
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- PSEL:
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access: rw
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description: Post-divider division ratio P
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lsb: 8
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reset_value: '0x1'
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width: 2
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- NSEL:
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access: rw
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description: Pre-divider division ratio N
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lsb: 12
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reset_value: '0x2'
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width: 2
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- MSEL:
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access: rw
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description: Feedback-divider division ratio (M)
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lsb: 16
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reset_value: '0x18'
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width: 8
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- CLK_SEL:
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access: rw
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description: Clock-source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_IDIVA_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: Integer divider power down
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lsb: 0
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reset_value: '0'
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width: 1
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- IDIV:
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access: rw
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description: Integer divider A divider value (1/(IDIV + 1))
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lsb: 2
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reset_value: '0x0'
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width: 2
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_IDIVB_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: Integer divider power down
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lsb: 0
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reset_value: '0'
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width: 1
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- IDIV:
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access: rw
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description: Integer divider B divider value (1/(IDIV + 1))
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lsb: 2
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reset_value: '0x0'
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width: 4
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_IDIVC_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: Integer divider power down
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lsb: 0
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reset_value: '0'
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width: 1
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- IDIV:
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access: rw
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description: Integer divider C divider value (1/(IDIV + 1))
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lsb: 2
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reset_value: '0x0'
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width: 4
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_IDIVD_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: Integer divider power down
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lsb: 0
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reset_value: '0'
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width: 1
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- IDIV:
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access: rw
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description: Integer divider D divider value (1/(IDIV + 1))
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lsb: 2
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reset_value: '0x0'
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width: 4
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_IDIVE_CTRL:
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fields: !!omap
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- PD:
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access: rw
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description: Integer divider power down
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lsb: 0
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reset_value: '0'
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width: 1
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- IDIV:
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access: rw
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description: Integer divider E divider value (1/(IDIV + 1))
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lsb: 2
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reset_value: '0x00'
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width: 8
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- AUTOBLOCK:
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access: rw
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: rw
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_BASE_SAFE_CLK:
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fields: !!omap
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- PD:
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access: r
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description: Output stage power down
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lsb: 0
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reset_value: '0'
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width: 1
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- AUTOBLOCK:
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access: r
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description: Block clock automatically during frequency change
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lsb: 11
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reset_value: '0'
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width: 1
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- CLK_SEL:
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access: r
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description: Clock source selection
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lsb: 24
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reset_value: '0x01'
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width: 5
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- CGU_BASE_USB0_CLK:
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fields: !!omap
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- PD:
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access: rw
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description: Output stage power down
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lsb: 0
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reset_value: '0'
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width: 1
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- AUTOBLOCK:
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access: rw
|
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description: Block clock automatically during frequency change
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lsb: 11
|
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reset_value: '0'
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width: 1
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- CLK_SEL:
|
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access: rw
|
|
description: Clock source selection
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lsb: 24
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reset_value: '0x07'
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width: 5
|
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- CGU_BASE_PERIPH_CLK:
|
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fields: !!omap
|
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- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
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lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
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- CGU_BASE_USB1_CLK:
|
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fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_M4_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_SPIFI_CLK:
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|
fields: !!omap
|
|
- PD:
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|
access: rw
|
|
description: Output stage power down
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|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
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|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_SPI_CLK:
|
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fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_PHY_RX_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_PHY_TX_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_APB1_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_APB3_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_LCD_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_VADC_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_SDIO_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_SSP0_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_SSP1_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_UART0_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_UART1_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_UART2_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_UART3_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_OUT_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_APLL_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_CGU_OUT0_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|
|
- CGU_BASE_CGU_OUT1_CLK:
|
|
fields: !!omap
|
|
- PD:
|
|
access: rw
|
|
description: Output stage power down
|
|
lsb: 0
|
|
reset_value: '0'
|
|
width: 1
|
|
- AUTOBLOCK:
|
|
access: rw
|
|
description: Block clock automatically during frequency change
|
|
lsb: 11
|
|
reset_value: '0'
|
|
width: 1
|
|
- CLK_SEL:
|
|
access: rw
|
|
description: Clock source selection
|
|
lsb: 24
|
|
reset_value: '0x01'
|
|
width: 5
|