321 lines
11 KiB
C
321 lines
11 KiB
C
/**
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* @brief GPIO definitions for the Qorvo PAC55xx series of microcontrollers.
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*
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* @addtogroup PAC55xx_gpio GPIO
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* @ingroup PAC55xx_defines
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* @author Brian Viele <vielster@allocor.tech>
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* LGPL License Terms @ref lgpl_license
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* @date 1 Dec 2019
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*
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* Definitions in this file come from the PAC55XX Family User Guide Rev 1.21
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* by Active-Semi dated August 26, 2019.
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef INCLUDE_LIBOPENCM3_PAC55XX_GPIO_H_
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#define INCLUDE_LIBOPENCM3_PAC55XX_GPIO_H_
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#include <libopencm3/cm3/common.h>
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/* Note: CCS include file defines pinmux, drive strength, pull-up/pull-down, etc. */
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#include <libopencm3/pac55xx/ccs.h>
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#include <libopencm3/pac55xx/memorymap.h>
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/**@{*/
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/** GPIO port base addresses (for convenience)
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* @defgroup gpio_port_id GPIO Port IDs
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* @{*/
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#define GPIOA GPIOA_BASE
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#define GPIOB GPIOB_BASE
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#define GPIOC GPIOC_BASE
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#define GPIOD GPIOD_BASE
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#define GPIOE GPIOE_BASE
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#define GPIOF GPIOF_BASE
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#define GPIOG GPIOG_BASE
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/**@}*/
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/** GPIO number definitions (for convenience)
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* @defgroup gpio_pin_id GPIO Pin Identifiers
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* @{*/
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#define GPIO_MAX_PIN (7U)
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#define GPIO0 BIT0
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#define GPIO1 BIT1
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#define GPIO2 BIT2
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#define GPIO3 BIT3
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#define GPIO4 BIT4
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#define GPIO5 BIT5
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#define GPIO6 BIT6
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#define GPIO7 BIT7
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#define GPIO_ALL 0xff
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/**@}*/
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/** GPIO Mode Register Definitions
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* @defgroup gpio_mode_regs GPIO MODE register mapping.
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* @{*/
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/* Enum definitions for at least minimal type safety. */
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typedef enum {
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GPIO_ANALOG_INPUT = 0,
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GPIO_PUSH_PULL_OUTPUT = 1,
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GPIO_OPEN_DRAIN_OUTPUT = 2,
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GPIO_HIGH_IMPEDENCE_INPUT = 3,
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} gpio_mode_t;
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#define GPIO_MODER(base) MMIO32((base) + 0x00)
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#define GPIOA_MODER GPIO_MODER(GPIOA)
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#define GPIOB_MODER GPIO_MODER(GPIOB)
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#define GPIOC_MODER GPIO_MODER(GPIOC)
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#define GPIOD_MODER GPIO_MODER(GPIOD)
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#define GPIOE_MODER GPIO_MODER(GPIOE)
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#define GPIOF_MODER GPIO_MODER(GPIOF)
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#define GPIOG_MODER GPIO_MODER(GPIOG)
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#define GPIO_MODER_MASK 0x3
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#define GPIO_MODER_MASK_PIN(pin) (GPIO_MODER_MASK << ((pin)*2))
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#define GPIO_MODER_MODE(pin, mode) (((mode)&GPIO_MODER_MASK) << ((pin)*2))
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/**@}*/
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/** GPIO Output Mask Register Definitions. This register may be used to lock the output value of
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* a pin as changes to masked pins will have no effect.
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* @defgroup gpio_outmask_regs GPIO OUTMASK register mapping.
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* @{*/
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#define GPIO_OUTMASKR(base) MMIO32((base) + 0x04)
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#define GPIOA_OUTMASKR GPIO_OUTMASKR(GPIOA)
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#define GPIOB_OUTMASKR GPIO_OUTMASKR(GPIOB)
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#define GPIOC_OUTMASKR GPIO_OUTMASKR(GPIOC)
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#define GPIOD_OUTMASKR GPIO_OUTMASKR(GPIOD)
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#define GPIOE_OUTMASKR GPIO_OUTMASKR(GPIOE)
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#define GPIOF_OUTMASKR GPIO_OUTMASKR(GPIOF)
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#define GPIOG_OUTMASKR GPIO_OUTMASKR(GPIOG)
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/**@}*/
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/** GPIO Output Register Definitions.
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* @defgroup gpio_out_regs GPIO OUT register mapping.
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* @{*/
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#define GPIO_OUTR(base) MMIO32((base) + 0x08)
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#define GPIOA_OUTR GPIO_OUTR(GPIOA)
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#define GPIOB_OUTR GPIO_OUTR(GPIOB)
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#define GPIOC_OUTR GPIO_OUTR(GPIOC)
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#define GPIOD_OUTR GPIO_OUTR(GPIOD)
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#define GPIOE_OUTR GPIO_OUTR(GPIOE)
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#define GPIOF_OUTR GPIO_OUTR(GPIOF)
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#define GPIOG_OUTR GPIO_OUTR(GPIOG)
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/**@}*/
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/** GPIO Input Register Definitions.
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* @defgroup gpio_in_regs GPIO IN register mapping.
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* @{*/
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#define GPIO_INR(base) MMIO32((base) + 0x0C)
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#define GPIOA_INR GPIO_INR(GPIOA)
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#define GPIOB_INR GPIO_INR(GPIOB)
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#define GPIOC_INR GPIO_INR(GPIOC)
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#define GPIOD_INR GPIO_INR(GPIOD)
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#define GPIOE_INR GPIO_INR(GPIOE)
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#define GPIOF_INR GPIO_INR(GPIOF)
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#define GPIOG_INR GPIO_INR(GPIOG)
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/**@}*/
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/** GPIO Interrupt Enable Register Definitions.
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* @defgroup gpio_inten_regs GPIO INTEN register mapping.
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* @{*/
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#define GPIO_INTENR(base) MMIO32((base) + 0x10)
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#define GPIOA_INTENR GPIO_INTENR(GPIOA)
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#define GPIOB_INTENR GPIO_INTENR(GPIOB)
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#define GPIOC_INTENR GPIO_INTENR(GPIOC)
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#define GPIOD_INTENR GPIO_INTENR(GPIOD)
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#define GPIOE_INTENR GPIO_INTENR(GPIOE)
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#define GPIOF_INTENR GPIO_INTENR(GPIOF)
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#define GPIOG_INTENR GPIO_INTENR(GPIOG)
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/**@}*/
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/** GPIO Interrupt Flag Register Definitions.
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* @defgroup gpio_intflag_regs GPIO INTFLAG register mapping.
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* @{*/
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#define GPIO_INTFLAGR(base) MMIO32((base) + 0x14)
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#define GPIOA_INTFLAGR GPIO_INTFLAGR(GPIOA)
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#define GPIOB_INTFLAGR GPIO_INTFLAGR(GPIOB)
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#define GPIOC_INTFLAGR GPIO_INTFLAGR(GPIOC)
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#define GPIOD_INTFLAGR GPIO_INTFLAGR(GPIOD)
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#define GPIOE_INTFLAGR GPIO_INTFLAGR(GPIOE)
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#define GPIOF_INTFLAGR GPIO_INTFLAGR(GPIOF)
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#define GPIOG_INTFLAGR GPIO_INTFLAGR(GPIOG)
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/**@}*/
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/** GPIO Interrupt Clear Register Definitions.
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* @defgroup gpio_intclear_regs GPIO INTCLEAR register mapping.
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* @{*/
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#define GPIO_INTCLEARR(base) MMIO32((base) + 0x1C)
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#define GPIOA_INTCLEARR GPIO_INTCLEARR(GPIOA)
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#define GPIOB_INTCLEARR GPIO_INTCLEARR(GPIOB)
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#define GPIOC_INTCLEARR GPIO_INTCLEARR(GPIOC)
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#define GPIOD_INTCLEARR GPIO_INTCLEARR(GPIOD)
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#define GPIOE_INTCLEARR GPIO_INTCLEARR(GPIOE)
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#define GPIOF_INTCLEARR GPIO_INTCLEARR(GPIOF)
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#define GPIOG_INTCLEARR GPIO_INTCLEARR(GPIOG)
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/**@}*/
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/** GPIO Interrupt Type Register Definitions.
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* @defgroup gpio_inttype_regs GPIO INTTYPE register mapping.
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* @{*/
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#define GPIO_INTTYPE_EDGE 0U
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#define GPIO_INTTYPE_LEVEL 1U
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#define GPIO_INTTYPER(base) MMIO32((base) + 0x20)
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#define GPIOA_INTTYPER GPIO_INTTYPER(GPIOA)
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#define GPIOB_INTTYPER GPIO_INTTYPER(GPIOB)
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#define GPIOC_INTTYPER GPIO_INTTYPER(GPIOC)
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#define GPIOD_INTTYPER GPIO_INTTYPER(GPIOD)
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#define GPIOE_INTTYPER GPIO_INTTYPER(GPIOE)
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#define GPIOF_INTTYPER GPIO_INTTYPER(GPIOF)
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#define GPIOG_INTTYPER GPIO_INTTYPER(GPIOG)
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/**@}*/
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/** GPIO Interrupt Config Register Definitions.
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* @defgroup gpio_intcfg_regs GPIO INTCFG register mapping.
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* @{*/
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#define GPIO_INTCFG_FALLING_LOW 0U
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#define GPIO_INTCFG_RISING_HIGH 1U
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#define GPIO_INTCFGR(base) MMIO32((base) + 0x24)
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#define GPIOA_INTCFGR GPIO_INTCFGR(GPIOA)
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#define GPIOB_INTCFGR GPIO_INTCFGR(GPIOB)
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#define GPIOC_INTCFGR GPIO_INTCFGR(GPIOC)
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#define GPIOD_INTCFGR GPIO_INTCFGR(GPIOD)
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#define GPIOE_INTCFGR GPIO_INTCFGR(GPIOE)
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#define GPIOF_INTCFGR GPIO_INTCFGR(GPIOF)
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#define GPIOG_INTCFGR GPIO_INTCFGR(GPIOG)
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/**@}*/
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/** GPIO Interrupt Edge Both Definitions. This overrides the config if set.
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* @defgroup gpio_intedgeboth_regs GPIO INTEDGEBOTH register mapping.
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* @{*/
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#define GPIO_INTEDGEBOTHR(base) MMIO32((base) + 0x28)
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#define GPIOA_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOA)
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#define GPIOB_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOB)
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#define GPIOC_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOC)
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#define GPIOD_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOD)
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#define GPIOE_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOE)
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#define GPIOF_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOF)
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#define GPIOG_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOG)
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/**@}*/
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/** GPIO Clock Synchronization Settings. When set, this enables 3-clock synchronizer on pins.
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* @defgroup gpio_clksync_regs GPIO CLKSYNC register mapping.
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* @{*/
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#define GPIO_CLKSYNCR(base) MMIO32((base) + 0x2C)
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#define GPIOA_CLKSYNCR GPIO_CLKSYNCR(GPIOA)
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#define GPIOB_CLKSYNCR GPIO_CLKSYNCR(GPIOB)
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#define GPIOC_CLKSYNCR GPIO_CLKSYNCR(GPIOC)
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#define GPIOD_CLKSYNCR GPIO_CLKSYNCR(GPIOD)
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#define GPIOE_CLKSYNCR GPIO_CLKSYNCR(GPIOE)
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#define GPIOF_CLKSYNCR GPIO_CLKSYNCR(GPIOF)
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#define GPIOG_CLKSYNCR GPIO_CLKSYNCR(GPIOG)
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/**@}*/
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/** GPIO Set Register. This register can be used for atomic setting of outputs.
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* @defgroup gpio_doset_regs GPIO DOSET register mapping.
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* @{*/
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#define GPIO_DOSETR(base) MMIO32((base) + 0x30)
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#define GPIOA_DOSETR GPIO_DOSETR(GPIOA)
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#define GPIOB_DOSETR GPIO_DOSETR(GPIOB)
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#define GPIOC_DOSETR GPIO_DOSETR(GPIOC)
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#define GPIOD_DOSETR GPIO_DOSETR(GPIOD)
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#define GPIOE_DOSETR GPIO_DOSETR(GPIOE)
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#define GPIOF_DOSETR GPIO_DOSETR(GPIOF)
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#define GPIOG_DOSETR GPIO_DOSETR(GPIOG)
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/**@}*/
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/** GPIO Set Register. This register can be used for atomic setting of outputs.
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* @defgroup gpio_doclear_regs GPIO DOCLEAR register mapping.
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* @{*/
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#define GPIO_DOCLEARR(base) MMIO32((base) + 0x34)
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#define GPIOA_DOCLEARR GPIO_DOCLEARR(GPIOA)
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#define GPIOB_DOCLEARR GPIO_DOCLEARR(GPIOB)
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#define GPIOC_DOCLEARR GPIO_DOCLEARR(GPIOC)
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#define GPIOD_DOCLEARR GPIO_DOCLEARR(GPIOD)
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#define GPIOE_DOCLEARR GPIO_DOCLEARR(GPIOE)
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#define GPIOF_DOCLEARR GPIO_DOCLEARR(GPIOF)
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#define GPIOG_DOCLEARR GPIO_DOCLEARR(GPIOG)
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/**@}*/
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/**@}*/
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BEGIN_DECLS
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/** GPIO Application Programming Interface.
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* @defgroup gpio_api GPIO Peripheral API
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* @ingroup peripheral_apis
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@{*/
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/**
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* Set the IO mode and pull-up/down configuration for the pins.
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* @param[in] gpioport Port to configure the alternate function on.
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* @param[in] mode IO Mode to configure (analog, input, output).
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* @param[in] pull_up_down Pull configuration (up/down/none) to set for the pins..
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* @param[in] gpios Pins to set with the mode and pull config specified.
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*/
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void gpio_mode_setup(uint32_t gpioport, gpio_mode_t mode,
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ccs_pull_updown_t pull_up_down, uint16_t gpios);
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/**
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* Set the output mask (disable changes) to the output pins specified.
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* @param[in] gpioport Port to set output mask on.
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* @param[in] enable Whether to enable or disable output masking.
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* @param[in] gpios bitfield of pins to set.
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*/
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void gpio_set_outmask(uint32_t gpioport, bool enable, uint16_t gpios);
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/**
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* Set the port pins specified to the true state.
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* @param[in] gpioport Port to set bits on.
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* @param[in] gpios bitfield of pins to set.
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*/
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void gpio_set(uint32_t gpioport, uint16_t gpios);
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/**
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* Clear the port pins specified to the false state.
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* @param[in] gpioport Port to clear bits on.
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* @param[in] gpios bitfield of pins to clear.
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*/
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void gpio_clear(uint32_t gpioport, uint16_t gpios);
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/**
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* Return a masked bitfield of the port specified.
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* @param[in] gpioport Port to read the bits from.
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* @param[in] gpios bitfield mask to apply to the port read.
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* @return masked bitfield of the port.
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*/
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uint16_t gpio_get(uint32_t gpioport, uint16_t gpios);
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/**
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* Set the function of the pin for this port. This will modify the pinmux,
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* @param[in] gpioport Port to configure the alternate function on.
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* @param[in] muxsel Mux select mode to configure on the port and pins.
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* @param[in] gpios Pins to set with the function specified.
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*/
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void gpio_set_af(uint32_t gpioport, ccs_muxsel_func_t muxsel, uint16_t gpios);
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/**
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* Set special output options for the gpio pin. For this MCU, this is only the drive strength.
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* @param[in] gpioport Port to configure the alternate function on.
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* @param[in] strength Drive strength (DS_XXMA from ccs.h).
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* @param[in] gpios Pins to set with the drive strength specified.
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*/
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void gpio_set_output_options(uint32_t gpioport, ccs_drive_strength_t strength,
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uint16_t gpios);
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/**
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* Set input schmidt trigger for glitch rejection on the input pin.
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* @param[in] gpioport Port to configure the alternate function on.
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* @param[in] enable True to enable, false to disable the schmidt trigger.
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* @param[in] gpios Pins to set with the schmidt trigger setting specified.
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*/
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void gpio_set_schmidt_trigger(uint32_t gpioport, bool enable, uint16_t gpios);
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/**@}*/
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END_DECLS
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#endif /* INCLUDE_LIBOPENCM3_PAC55XX_GPIO_H_ */
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