355 lines
14 KiB
C
355 lines
14 KiB
C
/** @defgroup creg_defines Configuration Registers Defines
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@brief <b>Defined Constants and Types for the LPC43xx Configuration
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Registers</b>
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@ingroup LPC43xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
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@date 10 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_CREG_H
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#define LPC43XX_CREG_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- CREG registers ----------------------------------------------------- */
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/*
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* Chip configuration register 32 kHz oscillator output and BOD control
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* register
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*/
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#define CREG_CREG0 MMIO32(CREG_BASE + 0x004)
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/* ARM Cortex-M4 memory mapping */
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#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)
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/* Chip configuration register 1 */
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#define CREG_CREG1 MMIO32(CREG_BASE + 0x108)
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/* Chip configuration register 2 */
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#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C)
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/* Chip configuration register 3 */
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#define CREG_CREG3 MMIO32(CREG_BASE + 0x110)
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/* Chip configuration register 4 */
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#define CREG_CREG4 MMIO32(CREG_BASE + 0x114)
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/* Chip configuration register 5 */
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#define CREG_CREG5 MMIO32(CREG_BASE + 0x118)
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/* DMA muxing control */
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#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)
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/* Flash accelerator configuration register for flash bank A */
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#define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120)
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/* Flash accelerator configuration register for flash bank B */
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#define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124)
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/* ETB RAM configuration */
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#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128)
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/*
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* Chip configuration register 6. Controls multiple functions: Ethernet
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* interface, SCT output, I2S0/1 inputs, EMC clock.
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*/
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#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C)
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/* Cortex-M4 TXEV event clear */
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#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)
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/* Part ID (Boundary scan ID code, read-only) */
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#define CREG_CHIPID MMIO32(CREG_BASE + 0x200)
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/* Cortex-M0 TXEV event clear */
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#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)
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/* ARM Cortex-M0 memory mapping */
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#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)
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/* USB0 frame length adjust register */
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#define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500)
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/* USB1 frame length adjust register */
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#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600)
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/* --- CREG_CREG0 values ---------------------------------------- */
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/* EN1KHZ: Enable 1 kHz output */
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#define CREG_CREG0_EN1KHZ_SHIFT (0)
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#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT)
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/* EN32KHZ: Enable 32 kHz output */
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#define CREG_CREG0_EN32KHZ_SHIFT (1)
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#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT)
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/* RESET32KHZ: 32 kHz oscillator reset */
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#define CREG_CREG0_RESET32KHZ_SHIFT (2)
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#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT)
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/* PD32KHZ: 32 kHz power control */
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#define CREG_CREG0_PD32KHZ_SHIFT (3)
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#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT)
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/* USB0PHY: USB0 PHY power control */
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#define CREG_CREG0_USB0PHY_SHIFT (5)
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#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT)
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/* ALARMCTRL: RTC_ALARM pin output control */
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#define CREG_CREG0_ALARMCTRL_SHIFT (6)
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#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT)
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#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT)
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/* BODLVL1: BOD trip level to generate an interrupt */
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#define CREG_CREG0_BODLVL1_SHIFT (8)
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#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT)
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#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT)
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/* BODLVL2: BOD trip level to generate a reset */
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#define CREG_CREG0_BODLVL2_SHIFT (10)
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#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT)
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#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT)
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/* SAMPLECTRL: SAMPLE pin input/output control */
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#define CREG_CREG0_SAMPLECTRL_SHIFT (12)
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#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT)
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#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT)
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/* WAKEUP0CTRL: WAKEUP0 pin input/output control */
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#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14)
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#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT)
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#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT)
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/* WAKEUP1CTRL: WAKEUP1 pin input/output control */
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#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16)
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#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT)
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#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT)
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/* --- CREG_M4MEMMAP values ------------------------------------- */
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/* M4MAP: Shadow address when accessing memory at address 0x00000000 */
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#define CREG_M4MEMMAP_M4MAP_SHIFT (12)
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#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT)
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#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT)
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/* --- CREG_CREG5 values ---------------------------------------- */
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/* M4TAPSEL: JTAG debug select for M4 core */
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#define CREG_CREG5_M4TAPSEL_SHIFT (6)
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#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT)
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/* M0APPTAPSEL: JTAG debug select for M0 co-processor */
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#define CREG_CREG5_M0APPTAPSEL_SHIFT (9)
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#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT)
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/* --- CREG_DMAMUX values --------------------------------------- */
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/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */
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#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0)
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#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT)
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/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */
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#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2)
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#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT)
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/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */
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#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4)
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#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT)
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/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */
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#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6)
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#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT)
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/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */
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#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8)
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#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT)
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/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */
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#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10)
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#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT)
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/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */
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#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12)
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#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT)
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/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */
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#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14)
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#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT)
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/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */
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#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16)
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#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT)
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/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */
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#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18)
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#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT)
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/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */
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#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20)
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#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT)
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/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */
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#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22)
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#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT)
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/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */
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#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24)
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#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT)
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/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */
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#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26)
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#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT)
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/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */
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#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28)
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#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT)
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/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */
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#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30)
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#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT)
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#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT)
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/* --- CREG_FLASHCFGA values ------------------------------------ */
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/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number
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* of BASE_M4_CLK clocks used for a flash access */
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#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12)
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#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT)
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#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT)
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/* POW: Flash bank A power control */
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#define CREG_FLASHCFGA_POW_SHIFT (31)
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#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT)
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/* --- CREG_FLASHCFGB values ------------------------------------ */
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/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number
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* of BASE_M4_CLK clocks used for a flash access */
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#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12)
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#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT)
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#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT)
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/* POW: Flash bank B power control */
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#define CREG_FLASHCFGB_POW_SHIFT (31)
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#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT)
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/* --- CREG_ETBCFG values --------------------------------------- */
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/* ETB: Select SRAM interface */
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#define CREG_ETBCFG_ETB_SHIFT (0)
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#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT)
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/* --- CREG_CREG6 values ---------------------------------------- */
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/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the
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* PHY interface */
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#define CREG_CREG6_ETHMODE_SHIFT (0)
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#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT)
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#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT)
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/* CTOUTCTRL: Selects the functionality of the SCT outputs */
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#define CREG_CREG6_CTOUTCTRL_SHIFT (4)
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#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT)
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/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */
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#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12)
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#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT)
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/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */
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#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13)
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#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT)
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/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */
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#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14)
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#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT)
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/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */
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#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15)
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#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT)
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/* EMC_CLK_SEL: EMC_CLK divided clock select */
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#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16)
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#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT)
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/* --- CREG_M4TXEVENT values ------------------------------------ */
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/* TXEVCLR: Cortex-M4 TXEV event */
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#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0)
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#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT)
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/* --- CREG_M0TXEVENT values ------------------------------------ */
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/* TXEVCLR: Cortex-M0 TXEV event */
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#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0)
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#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT)
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/* --- CREG_M0APPMEMMAP values ---------------------------------- */
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/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */
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#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12)
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#define CREG_M0APPMEMMAP_M0APPMAP_MASK \
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(0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
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#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
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/* --- CREG_USB0FLADJ values ------------------------------------ */
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/* FLTV: Frame length timing value */
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#define CREG_USB0FLADJ_FLTV_SHIFT (0)
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#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT)
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#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT)
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/* --- CREG_USB1FLADJ values ------------------------------------ */
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/* FLTV: Frame length timing value */
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#define CREG_USB1FLADJ_FLTV_SHIFT (0)
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#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT)
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#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT)
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/**@}*/
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#endif
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