551 lines
17 KiB
C
551 lines
17 KiB
C
/** @defgroup uart_defines UART Control
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*
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* @brief <b>Defined Constants and Types for the LM4F UART Control</b>
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*
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* @ingroup LM4Fxx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2013
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* Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* @date 07 May 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_LM4F_UART_H
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#define LIBOPENCM3_LM4F_UART_H
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/**@{*/
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#include <libopencm3/lm4f/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* =============================================================================
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* Convenience macros
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* ---------------------------------------------------------------------------*/
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/** @defgroup uart_reg_base UART register base addresses
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* @{*/
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#define UART0 UART0_BASE
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#define UART1 UART1_BASE
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#define UART2 UART2_BASE
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#define UART3 UART3_BASE
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#define UART4 UART4_BASE
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#define UART5 UART5_BASE
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#define UART6 UART6_BASE
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#define UART7 UART7_BASE
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/** @} */
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/* =============================================================================
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* UART registers
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* ---------------------------------------------------------------------------*/
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/* UART data register */
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#define UART_DR(uart_base) MMIO32((uart_base) + 0x00)
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/* UART Receive Status/Error Clear register */
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#define UART_RSR(uart_base) MMIO32((uart_base) + 0x04)
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#define UART_ECR(uart_base) MMIO32((uart_base) + 0x04)
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/* UART Flag register */
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#define UART_FR(uart_base) MMIO32((uart_base) + 0x18)
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/* UART IrDA Low-Power register */
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#define UART_ILPR(uart_base) MMIO32((uart_base) + 0x20)
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/* UART Integer baudrate divisor */
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#define UART_IBRD(uart_base) MMIO32((uart_base) + 0x24)
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/* UART Fractional baudrate divisor */
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#define UART_FBRD(uart_base) MMIO32((uart_base) + 0x28)
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/* UART Line control */
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#define UART_LCRH(uart_base) MMIO32((uart_base) + 0x2C)
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/* UART Control */
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#define UART_CTL(uart_base) MMIO32((uart_base) + 0x30)
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/* UART Interrupt FIFO level select */
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#define UART_IFLS(uart_base) MMIO32((uart_base) + 0x34)
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/* UART Interrupt mask */
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#define UART_IM(uart_base) MMIO32((uart_base) + 0x38)
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/* UART Raw interrupt status */
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#define UART_RIS(uart_base) MMIO32((uart_base) + 0x3C)
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/* UART Masked Interrupt status */
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#define UART_MIS(uart_base) MMIO32((uart_base) + 0x40)
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/* UART Interrupt Clear */
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#define UART_ICR(uart_base) MMIO32((uart_base) + 0x44)
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/* UART DMA control */
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#define UART_DMACTL(uart_base) MMIO32((uart_base) + 0x48)
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/* UART LIN control */
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#define UART_LCTL(uart_base) MMIO32((uart_base) + 0x90)
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/* UART LIN snap shot */
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#define UART_LSS(uart_base) MMIO32((uart_base) + 0x94)
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/* UART LIN timer */
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#define UART_LTIM(uart_base) MMIO32((uart_base) + 0x98)
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/* UART 9-Bit self address */
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#define UART_9BITADDR(uart_base) MMIO32((uart_base) + 0xA4)
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/* UART 9-Bit self address mask */
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#define UART_9BITAMASK(uart_base) MMIO32((uart_base) + 0xA8)
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/* UART Peripheral properties */
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#define UART_PP(uart_base) MMIO32((uart_base) + 0xFC0)
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/* UART Clock configuration */
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#define UART_CC(uart_base) MMIO32((uart_base) + 0xFC8)
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/* UART Peripheral Identification 4 */
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#define UART_PERIPH_ID4(uart_base) MMIO32((uart_base) + 0xFD0)
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/* UART Peripheral Identification 5 */
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#define UART_PERIPH_ID5(uart_base) MMIO32((uart_base) + 0xFD4)
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/* UART Peripheral Identification 6 */
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#define UART_PERIPH_ID6(uart_base) MMIO32((uart_base) + 0xFD8)
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/* UART Peripheral Identification 7 */
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#define UART_PERIPH_ID7(uart_base) MMIO32((uart_base) + 0xFDC)
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/* UART Peripheral Identification 0 */
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#define UART_PERIPH_ID0(uart_base) MMIO32((uart_base) + 0xFE0)
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/* UART Peripheral Identification 1 */
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#define UART_PERIPH_ID1(uart_base) MMIO32((uart_base) + 0xFE4)
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/* UART Peripheral Identification 2 */
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#define UART_PERIPH_ID2(uart_base) MMIO32((uart_base) + 0xFE8)
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/* UART Peripheral Identification 3 */
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#define UART_PERIPH_ID3(uart_base) MMIO32((uart_base) + 0xFEC)
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/* UART PrimeCell Identification 0 */
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#define UART_PCELL_ID0(uart_base) MMIO32((uart_base) + 0xFF0)
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/* UART PrimeCell Identification 1 */
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#define UART_PCELL_ID1(uart_base) MMIO32((uart_base) + 0xFF4)
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/* UART PrimeCell Identification 2 */
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#define UART_PCELL_ID2(uart_base) MMIO32((uart_base) + 0xFF8)
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/* UART PrimeCell Identification 3 */
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#define UART_PCELL_ID3(uart_base) MMIO32((uart_base) + 0xFFC)
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/* =============================================================================
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* UART_DR values
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* ---------------------------------------------------------------------------*/
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/** Overrun Error */
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#define UART_DR_OE (1 << 11)
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/** Break Error */
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#define UART_DR_BE (1 << 10)
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/** Parity Error */
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#define UART_DR_PE (1 << 9)
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/** Framing Error */
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#define UART_DR_FE (1 << 8)
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/** Data transmitted or received */
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#define UART_DR_DATA_MASK (0xFF << 0)
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/* =============================================================================
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* Readonly UART_RSR values
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* ---------------------------------------------------------------------------*/
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/** Overrun Error */
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#define UART_RSR_OE (1 << 3)
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/** Break Error */
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#define UART_RSR_BE (1 << 2)
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/** Parity Error */
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#define UART_RSR_PE (1 << 1)
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/** Framing Error */
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#define UART_RSR_FE (1 << 0)
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/* =============================================================================
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* UART_FR values
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* ---------------------------------------------------------------------------*/
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/** Tx FIFO empty */
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#define UART_FR_TXFE (1 << 7)
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/** Rx FIFO full */
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#define UART_FR_RXFF (1 << 6)
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/** Tx FIFO full */
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#define UART_FR_TXFF (1 << 5)
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/** Rx FIFO empty */
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#define UART_FR_RXFE (1 << 4)
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/** UART Busy */
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#define UART_FR_BUSY (1 << 3)
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/** Clear To Send */
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#define UART_FR_CTS (1 << 0)
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/* =============================================================================
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* UART_LCRH values
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* ---------------------------------------------------------------------------*/
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/** Stick parity select */
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#define UART_LCRH_SPS (1 << 7)
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/** Word length */
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#define UART_LCRH_WLEN_MASK (3 << 5)
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#define UART_LCRH_WLEN_5 (0 << 5)
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#define UART_LCRH_WLEN_6 (1 << 5)
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#define UART_LCRH_WLEN_7 (2 << 5)
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#define UART_LCRH_WLEN_8 (3 << 5)
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/** Enable FIFOs */
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#define UART_LCRH_FEN (1 << 4)
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/** Two stop bits select */
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#define UART_LCRH_STP2 (1 << 3)
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/** Even parity select */
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#define UART_LCRH_EPS (1 << 2)
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/** Parity enable */
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#define UART_LCRH_PEN (1 << 1)
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/** Send break */
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#define UART_LCRH_BRK (1 << 0)
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/* =============================================================================
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* UART_CTL values
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* ---------------------------------------------------------------------------*/
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/** Enable Clear To Send */
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#define UART_CTL_CTSEN (1 << 15)
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/** Enable Request To Send */
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#define UART_CTL_RTSEN (1 << 14)
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/** Request To Send */
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#define UART_CTL_RTS (1 << 11)
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/** Data terminal ready */
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#define UART_CTL_DTR (1 << 10)
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/** Rx Enable */
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#define UART_CTL_RXE (1 << 9)
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/** Tx Enable */
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#define UART_CTL_TXE (1 << 8)
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/** Loop back enable */
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#define UART_CTL_LBE (1 << 7)
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/** LIN mode enable */
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#define UART_CTL_LIN (1 << 6)
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/** High speed Enable */
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#define UART_CTL_HSE (1 << 5)
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/** End of transmission */
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#define UART_CTL_EOT (1 << 4)
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/** ISO 7816 Smart Card support */
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#define UART_CTL_SMART (1 << 3)
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/** SIR low-power mode */
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#define UART_CTL_SIRLIP (1 << 2)
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/** SIR enable */
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#define UART_CTL_SIREN (1 << 1)
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/** UART enable */
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#define UART_CTL_UARTEN (1 << 0)
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/* =============================================================================
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* UART_IFLS values
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* ---------------------------------------------------------------------------*/
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/** UART Rx interrupt FIFO level select */
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#define UART_IFLS_RXIFLSEL_MASK (7 << 3)
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#define UART_IFLS_RXIFLSEL_1_8 (0 << 3)
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#define UART_IFLS_RXIFLSEL_1_4 (1 << 3)
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#define UART_IFLS_RXIFLSEL_1_2 (2 << 3)
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#define UART_IFLS_RXIFLSEL_3_4 (3 << 3)
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#define UART_IFLS_RXIFLSEL_7_8 (4 << 3)
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/** UART Tx interrupt FIFO level select */
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#define UART_IFLS_TXIFLSEL_MASK (7 << 0)
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#define UART_IFLS_TXIFLSEL_7_8 (0 << 0)
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#define UART_IFLS_TXIFLSEL_3_4 (1 << 0)
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#define UART_IFLS_TXIFLSEL_1_2 (2 << 0)
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#define UART_IFLS_TXIFLSEL_1_4 (3 << 0)
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#define UART_IFLS_TXIFLSEL_1_8 (4 << 0)
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/* =============================================================================
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* UART interrupt mask values
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*
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* These are interchangeable across UART_IM, UART_RIS, UART_MIS, and UART_ICR
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* registers.
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* ---------------------------------------------------------------------------*/
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/** LIN mode edge 5 interrupt mask */
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#define UART_IM_LME5IM (1 << 15)
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/** LIN mode edge 1 interrupt mask */
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#define UART_IM_LME1IM (1 << 14)
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/** LIN mode sync break interrupt mask */
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#define UART_IM_LMSBIM (1 << 13)
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/** 9-bit mode interrupt mask */
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#define UART_IM_9BITIM (1 << 12)
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/** Overrun error interrupt mask */
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#define UART_IM_OEIM (1 << 10)
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/** Break error interrupt mask */
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#define UART_IM_BEIM (1 << 9)
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/** Parity error interrupt mask */
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#define UART_IM_PEIM (1 << 8)
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/** Framing error interrupt mask */
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#define UART_IM_FEIM (1 << 7)
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/** Receive time-out interrupt mask */
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#define UART_IM_RTIM (1 << 6)
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/** Transmit interrupt mask */
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#define UART_IM_TXIM (1 << 5)
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/** Receive interrupt mask */
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#define UART_IM_RXIM (1 << 4)
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/** Data Set Ready modem interrupt mask */
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#define UART_IM_DSRIM (1 << 3)
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/** Data Carrier Detect modem interrupt mask */
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#define UART_IM_DCDIM (1 << 2)
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/** Clear To Send modem interrupt mask */
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#define UART_IM_CTSIM (1 << 1)
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/** Ring Indicator modem interrupt mask */
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#define UART_IM_RIIM (1 << 0)
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/* =============================================================================
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* UART_DMACTL values
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* ---------------------------------------------------------------------------*/
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/** DMA on error */
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#define UART_DMACTL_DMAERR (1 << 2)
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/** Transmit DMA enable */
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#define UART_DMACTL_TXDMAE (1 << 1)
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/** Receive DMA enable */
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#define UART_DMACTL_RXDMAE (1 << 0)
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/* =============================================================================
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* UART_LCTL values
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* ---------------------------------------------------------------------------*/
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/** Sync break length */
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#define UART_LCTL_BLEN_MASK (3 << 4)
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#define UART_LCTL_BLEN_16T (3 << 4)
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#define UART_LCTL_BLEN_15T (2 << 4)
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#define UART_LCTL_BLEN_14T (1 << 4)
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#define UART_LCTL_BLEN_13T (0 << 4)
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/** LIN master enable */
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#define UART_LCTL_MASTER (1 << 0)
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/* =============================================================================
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* UART_9BITADDR values
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* ---------------------------------------------------------------------------*/
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/** Enable 9-bit mode */
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#define UART_UART_9BITADDR_9BITEN (1 << 15)
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/** Self-address for 9-bit mode */
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#define UART_UART_9BITADDR_ADDR_MASK (0xFF << 0)
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/* =============================================================================
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* UART_PP values
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* ---------------------------------------------------------------------------*/
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/** 9-bit support */
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#define UART_UART_PP_NB (1 << 1)
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/** Smart Card support */
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#define UART_UART_PP_SC (1 << 0)
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/* =============================================================================
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* UART_CC values
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* ---------------------------------------------------------------------------*/
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/** UART baud clock source */
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#define UART_CC_CS_MASK (0xF << 0)
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#define UART_CC_CS_SYSCLK (0x0 << 0)
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#define UART_CC_CS_PIOSC (0x5 << 0)
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/* =============================================================================
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* Convenience enums
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* ---------------------------------------------------------------------------*/
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enum uart_parity {
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UART_PARITY_NONE,
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UART_PARITY_ODD,
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UART_PARITY_EVEN,
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UART_PARITY_STICK_0,
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UART_PARITY_STICK_1,
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};
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enum uart_flowctl {
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UART_FLOWCTL_NONE,
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UART_FLOWCTL_RTS,
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UART_FLOWCTL_CTS,
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UART_FLOWCTL_RTS_CTS,
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};
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/**
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* \brief UART interrupt masks
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*
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* These masks can be OR'ed together to specify more than one interrupt. For
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* example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt.
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*/
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enum uart_interrupt_flag {
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UART_INT_LME5 = UART_IM_LME5IM,
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UART_INT_LME1 = UART_IM_LME1IM,
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UART_INT_LMSB = UART_IM_LMSBIM,
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UART_INT_9BIT = UART_IM_9BITIM,
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UART_INT_OE = UART_IM_OEIM,
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UART_INT_BE = UART_IM_BEIM,
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UART_INT_PE = UART_IM_PEIM,
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UART_INT_FE = UART_IM_FEIM,
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UART_INT_RT = UART_IM_RTIM,
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UART_INT_TX = UART_IM_TXIM,
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UART_INT_RX = UART_IM_RXIM,
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UART_INT_DSR = UART_IM_DSRIM,
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UART_INT_DCD = UART_IM_DCDIM,
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UART_INT_CTS = UART_IM_CTSIM,
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UART_INT_RI = UART_IM_RIIM,
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};
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/**
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* \brief UART RX FIFO interrupt trigger levels
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*
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* The levels indicate how full the FIFO should be before an interrupt is
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* generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when
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* the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being
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* triggered by a single character.
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*/
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enum uart_fifo_rx_trigger_level {
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UART_FIFO_RX_TRIG_1_8 = UART_IFLS_RXIFLSEL_1_8,
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UART_FIFO_RX_TRIG_1_4 = UART_IFLS_RXIFLSEL_1_4,
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UART_FIFO_RX_TRIG_1_2 = UART_IFLS_RXIFLSEL_1_2,
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UART_FIFO_RX_TRIG_3_4 = UART_IFLS_RXIFLSEL_3_4,
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UART_FIFO_RX_TRIG_7_8 = UART_IFLS_RXIFLSEL_7_8
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};
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/**
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* \brief UART TX FIFO interrupt trigger levels
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*
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* The levels indicate how empty the FIFO should be before an interrupt is
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* generated. Note that this indicates the emptiness of the FIFO and not the
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* fullness. This is somewhat confusing, but it follows the wording of the
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* LM4F120H5QR datasheet.
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*
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* UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is
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* 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered
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* by a single character.
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*/
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enum uart_fifo_tx_trigger_level {
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UART_FIFO_TX_TRIG_7_8 = UART_IFLS_TXIFLSEL_7_8,
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UART_FIFO_TX_TRIG_3_4 = UART_IFLS_TXIFLSEL_3_4,
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UART_FIFO_TX_TRIG_1_2 = UART_IFLS_TXIFLSEL_1_2,
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UART_FIFO_TX_TRIG_1_4 = UART_IFLS_TXIFLSEL_1_4,
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UART_FIFO_TX_TRIG_1_8 = UART_IFLS_TXIFLSEL_1_8
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};
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/* =============================================================================
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* Function prototypes
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* ---------------------------------------------------------------------------*/
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BEGIN_DECLS
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void uart_set_baudrate(uint32_t uart, uint32_t baud);
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void uart_set_databits(uint32_t uart, uint8_t databits);
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void uart_set_stopbits(uint32_t uart, uint8_t stopbits);
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void uart_set_parity(uint32_t uart, enum uart_parity parity);
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void uart_set_mode(uint32_t uart, uint32_t mode);
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void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow);
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void uart_enable(uint32_t uart);
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void uart_disable(uint32_t uart);
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void uart_clock_from_piosc(uint32_t uart);
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void uart_clock_from_sysclk(uint32_t uart);
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void uart_send(uint32_t uart, uint16_t data);
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uint16_t uart_recv(uint32_t uart);
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void uart_wait_send_ready(uint32_t uart);
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void uart_wait_recv_ready(uint32_t uart);
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void uart_send_blocking(uint32_t uart, uint16_t data);
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uint16_t uart_recv_blocking(uint32_t uart);
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void uart_enable_rx_dma(uint32_t uart);
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void uart_disable_rx_dma(uint32_t uart);
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void uart_enable_tx_dma(uint32_t uart);
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void uart_disable_tx_dma(uint32_t uart);
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void uart_enable_fifo(uint32_t uart);
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void uart_disable_fifo(uint32_t uart);
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void uart_set_fifo_trigger_levels(uint32_t uart,
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enum uart_fifo_rx_trigger_level rx_level,
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enum uart_fifo_tx_trigger_level tx_level);
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/* We inline FIFO full/empty checks as they are intended to be called from ISRs
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* */
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/** @ingroup uart_fifo
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* @{
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* \brief Determine if the TX fifo is full
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*
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* @param[in] uart UART block register address base @ref uart_reg_base
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*/
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static inline
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bool uart_is_tx_fifo_full(uint32_t uart)
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{
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return UART_FR(uart) & UART_FR_TXFF;
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}
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/**
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* \brief Determine if the TX fifo is empty
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*
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* @param[in] uart UART block register address base @ref uart_reg_base
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*/
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static inline
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bool uart_is_tx_fifo_empty(uint32_t uart)
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{
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return UART_FR(uart) & UART_FR_TXFE;
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}
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/**
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* \brief Determine if the RX fifo is full
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*
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* @param[in] uart UART block register address base @ref uart_reg_base
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*/
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static inline
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bool uart_is_rx_fifo_full(uint32_t uart)
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|
{
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return UART_FR(uart) & UART_FR_RXFF;
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}
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|
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/**
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* \brief Determine if the RX fifo is empty
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|
*
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* @param[in] uart UART block register address base @ref uart_reg_base
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|
*/
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static inline
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bool uart_is_rx_fifo_empty(uint32_t uart)
|
|
{
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|
return UART_FR(uart) & UART_FR_RXFE;
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}
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/**@}*/
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|
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void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
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void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
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void uart_enable_rx_interrupt(uint32_t uart);
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|
void uart_disable_rx_interrupt(uint32_t uart);
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|
void uart_enable_tx_interrupt(uint32_t uart);
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|
void uart_disable_tx_interrupt(uint32_t uart);
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|
void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints);
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|
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|
/* Let's keep this one inlined. It's designed to be used in ISRs */
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|
/** @ingroup uart_irq
|
|
* @{
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|
* \brief Determine if interrupt is generated by the given source
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|
*
|
|
* @param[in] uart UART block register address base @ref uart_reg_base
|
|
* @param[in] source source to check.
|
|
*/
|
|
static inline
|
|
bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source)
|
|
{
|
|
return UART_MIS(uart) & source;
|
|
}
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|
/**@}*/
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|
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|
END_DECLS
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|
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|
/**@}*/
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|
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#endif /* LIBOPENCM3_LM4F_UART_H */
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