Wrong since original commit in 2013.
LCD code can't actually automatically determine clock speed if it's HSE,
as we don't know here whether what HSE is, nor what it's divided by.
For more fun, that old 2014 API doesn't have any way of flagging that it
failed either. Hooray.
We did have
* _HPRE_SYSCLK_DIVN (3 parts)
* _HPRE_DIVN (5 parts)
* _HPRE_DIV_N (4 parts)
Unify all on _HPRE_DIVN. Provide deprecated definitions to not break
everything at once.
Also, standardize on "NODIV" instead of DIVNONE.
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
Originally suggested in https://github.com/libopencm3/libopencm3/pull/399
At least provide macros for each family that allows easy masking of the
full set of reset reason flags. Trying to provide a function that
provides these in random upper bits seems unclear at best.
Some parts used HSICLK, some used HSI. Most used NOCLK, f3 used
DISABLED. Try and move all to the shorter, simpler forms, instead of
having mixed defines for different targets for the same thing. Just
because the bits themselves are different doesn't mean we should make it
more difficult for users to port code.
MCOPRE prescaler definitions used a _SHIFT and a preshiftd definition.
The rest of the file uses separate _MASK and _SHIFT definitions.
Fix whitespace on the definitions while we're here.
Original implementation only checked whether the user had _selected_ the
clock, not whether it had actually switched to the clock or not. For
almost all cases, this made this function either a no-op, if you _had_
selected the clock, or a blocking loop if you hadn't selected it ahead
of time.
Fixes github issue #687
Original commits, while appearing clean and tidy, hadn't even been
compile tested. Trust no-one. Not even Scully.
Fixes: 770878e7b4
Fixes: 86d20ef00c
Fixes: 05ff0df322
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
This adds MCO source selection to some targets, and removes and standardizes
the mask/shift usage for all targets. For devices that support MCO2, this
supports only MCO1. No attempt has been made to extract MCO prescaler, which
is not available on all F1 and F3.
Rename rcc_ppre1_frequency and rcc_ppre2_frequency to rcc_apb1_frequency and rcc_apb2_frequency
Also add rcc_ahb_frequency (although it is not set correctly in all cases) which will be fixed by
the rcc commits later. Also fixup the only use in the library of these variables, the USART code.
And fix the typos that resulted
Make l1 generic too
to remove variations, redundancies, add missing, fix errors. All c files
refer only to the dispatch style headers in /include/stm32. Those headers
#include memorymap.h and cm3/common.h. All references to
these are removed from the family specific headers. Ethernet untouched as
it appears incomplete.
Added dummy spi.c for F0/F3. Fix some doxygen anomalies.
So that the navigation pane works correctly in browsers.
Some additional doc fixes put in where found (but many more still to go).
Added some dummy .c and .h files to bring the associated docs into line.
makefile changed to allow 'make html' as well as 'make doc' (the latter only does html anyway).
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
Add an example using the RTC to help with a lower power design. This is
a sister example to the existing "button-irq-printf", which is
functionally identical, but uses far less power.
There's more tricks that can be done to lower the power even further,
but this shows a few of the early steps that can be done, using the RTC
wakeup instead of a timer.
Code added for L1 to support the PWR Control block didn't properly
follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and
some headers were missing. This commit has no functional changes, it
only addresses the style and structure problems.
Despite the L1 being a low power device, my initial focus is on making
it basically compatible with existing devices.
To that end, provide clock setup helper routines that configure it for maximum performance,
allowing some similar clock speeds to F1 devices to help with testing. This requires adding
the power chipset routines to set the voltage range.
Clock setup style is similar to the F4 code, which seems nicer than the overflow of different
routines used on the F1 code.
NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power
code, even though it should be compatible
Karl Palsson