- Makefiles now include building f3 src directory.
- Gpio support added. gpio_common_f24 changed to support also f3.
- f3 still not compiling, but f2 compile not broken (probably also f4).
In places where we were defining memory mapped peripheral buffers we
were using directly a cast to "volatile int_type *". For consistency we
should use dereferenced accessor like: &MMIO32(address)
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
According to the reference manual, you are _forbidden_ from writing 00 to the
VOS[1:0] bits in PWR_CR. Writing a 00 is automatically turned into range 2,
or, 10. Attempting to then |= the bits for range 1 (01) results in the final
result of choosing voltage range 3 (11). This has fairly catastrophic effects
if you then attempt to switch to PLL clock at 32Mhz.
Oddly, the existing code was working fine on STM32L151C6 revision W, but
failing with revision V silicon. Regardless, the existing code was wrong and
not following the reference manual.
Further, attempting to change any power voltage range settings without the RCC
enabled will have no effect, so all the higher level helper routines
have added peripheral enable lines before attempting to set the range.
This switch to HSI was an attempt to run the setup code faster. However,
there's no real need for this, and it just confuses things by switching first
to one clock, and then to another. Just keep running on the existing clock
until switching to the clock actually chosen by the user's arguments.
Added hash processor register definitions and main functions. Hash
processor is supported in stm32f21, stm32f41 and stm32f43 and can be
used to calculate Md5 and Sha1.
Change flash_erase_sector (f2/f4) to take numerical sector argument.
As opposed to using one of the defines in the header, this is more convenient when programatically deciding which sectors to erase.
f1/timer.
Added timer_ic_set_polarity to timer_common_f24 with
the enum tim_ic_pol now including trigger on both edges.
Changed timer_slave_set_polarity to use enum tim_et_pol
rather than tim_ic_pol.
In response to suggestion of stinkydiver73 on 24 March that
timers in all families have an option for triggers on both
edges, except F1.
F2 and F4 have a common section to deal with the options register (TIM2 and TIM5 only)
L1 has been made common with timer_common_all as its options register has very different settings to F2/F4. Code is in the L1/timer.c L1/timer.h files
Note that F3 and F05 timers should fit into this scheme, with F3 having additional features.
Bundled with this is L1/pwr.h to change a documentation setting
Also all the Doxyfiles have added "ENABLE_PREPROCESSING = NO" to fix a problem introduced by commit 118.
(prevents inclusion and also issues warning)
Changes to some source files to remove references to common headers.
Changes to rng.h to make guard symbols the same in f2 and f4.
to remove errors, duplications and inconsistencies.
File lib/stm32/f1/pwr.c - all code removed as it duplicates that in common/pwr_common.c
Remaining changes do not affect code. Compiles OK.
TODO efm32 has no code so generates no modules
TODO F2 needs pwr.c
TODO L1 needs dma.h and dma.c
Clearing a single bit in DMA_CCR, then immediately writing a 0 over the
entire register is completely redundant on the F1, F3 and L1 DMA
peripherals. (Unlike the F2 & F4 DMA Peripheral, where this is
required)
Add an example using the RTC to help with a lower power design. This is
a sister example to the existing "button-irq-printf", which is
functionally identical, but uses far less power.
There's more tricks that can be done to lower the power even further,
but this shows a few of the early steps that can be done, using the RTC
wakeup instead of a timer.
Add the register definitions and some of the most basic helper functions
for the new style BCD RTC module found on the F2, F4, L1, F3 and F0.
This tries to keep as close to HACKING_COMMON_DOC as possible, while
maintaining sane names.
Code added for L1 to support the PWR Control block didn't properly
follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and
some headers were missing. This commit has no functional changes, it
only addresses the style and structure problems.
Earlier additions to the L1 support were not correctly using linux
coding guidelines as specified in /HACKING.
Some examples were also missing license information.
Updated the documentation so that it appears in all families
Also added it to the L1 area, but is untested. An addition to the memorymap
allows commonality and a #ifdef added to the spi_common_all code to
exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those.
An rcc dispatch header was added to remove same code from the spi header.
In the header:
- Fix DMA_SxCR_CT: change shift from 18 to 19
For use with the convenience functions:
- Added DMA_SxCR_CHSEL generic values
- Added DMA_STREAM - generic values
- Added dma_if_offset - rather than separating out LISR and HISR
- Added masks
- Added dma_disable_double_buffer_mode()
Federico Ruiz Ugalde