The STM32F05xxx/06xxx manual describes on p.98 (Sec 7.4.1) the RCC_CR
register, on which it says that bit 24 is the PLLON bit which has to be
enabled before using the PLL. This causes the PLL to be enabled with
rcc_osc_on(PLL).
According to RM0090, page 301, paragraph 11.13.12 Note. (For F4, for F1 and F3 is it in the corresponding manuals)
The JSQR are filled always ending at SQR4 ie for those lists we must set this list:
(A) -> JSQ4 = A,
(A,B) -> JSQ3 = A, JSQ4 = B,
(A,B,C) -> JSQ2 = A, JSQ3 = B, JSQ4 = C,
(A,B,C,D) -> JSQ1 = A, JSQ2 = B, JSQ3 = C, JSQ4 = D,
The readed values are in correct order, starting from JDR1:
(A) -> JDR1 = A,
(A,B) -> JDR1 = A, JDR2 = B,
(A,B,C) -> JDR1 = A, JDR2 = B, JDR3 = C,
(A,B,C,D) -> JDR1 = A, JDR2 = B, JDR3 = C, JDR4 = D,
The common code wasn't being included in L1 builds, even though the headers now
included the correct definitions.
This combines the two f0 and f3 spi files, which previously differed only in
the number of spi peripherals defined.
Files were renamed to the full "l1f124" style, not because I like it, but
because it's the convention we have, so it's best to apply it rigourously.
Tested on L1 and F100 boards, compile tested only for others, but the examples
repository all compiles too. (Though the lack of SPI examples for all
platforms was how this broke in the first place)
STM32L1 has a different set of offsets, not just a different base
address, so we can't have common registers definitions. Also, out of
F0,F1,F2,F3,F4,L1, only the F1 has the odd note about 2x16bit registers
and 2x32bit registers with one 16bit register marked as "This field
value is also reserved for a future feature." Therefore, replace the
awkward reading out as multiple words and just copy them in.
F0,F2,F3,F4 were missing definitions altogether.
This does _not_ attempt to address the problem of the mismatched base
addresses for Medium+ and High Density L1 parts.
We currently default to "-mfloat-abi=hard -mfpu=fpv4-sp-d16" for M4F cores, and
and variations of "-mfloat-abi=soft" for the others. Keep the M4F default, and
move others to no FP flags for consistency, but allow overriding these flags
via the FP_FLAGS environment variable.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Because most changes are internal to a function in exti.c I am leaving
the macro checks in there, otherwise we would end up with a bunch of
code duplication if we used the dispatch system used otherwise
throughout the stm32 part of the library. I bet it could be split up
into more granular functions resulting in more generic code that we
could run through the dispatch system. But I am leaving that as an
excersize for later.
We don't support f0 yet so let's not fool anyone. We may rename those
files back again if when we cross check that it is actually true this
file supports f0.
- Additional frequency configuration (48Mhz, for usb use!)
- FLASH latency decreased (too unnecessarily low before)
- Rcc functions to change usb freq prescaler.
- Several functions added (that only work on the f3)
- The data register now has a 8bit access counter part
that is necessary for 8bit transmissions, together with
the access functions.
- The init master functions doesn't work for the f3.
Very few functions can be shared (~ 3). A possible solutions is to move
i2c_common_all to i2c_common_f124, create i2c_common_all and move f3/i2c to i2c_common_f3. Who agrees?
- Makefiles of other stm32s updated accordingly.
- f3/rcc.c updated to some definition changes.
- f3/flash.c removed in order to use flash_common_f234.c to comply with new organization.
molnarkares