In adc_calibrate_async() we should only set the ADCAL bit and leave the rest alone.
While in the past there were only "rs" bits in this register, this is no
longer the case.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Generate doc root doxygenlayout file, as well as devices stuff, based on main
Makefile $(TARGETS) and template files. Avoids painfull sync/merge of 20 files+
when adding a new device.
bonus : allow to build only one device doc easily (make TARGETS=stm32f0 doc)
regression: we currently loose device "fancy" naming as device name is
guessed (toUpper()..) from folder name.
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.
Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.
From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage. We can
see where they move in the future.
Make exti_get_flag_status and exti_reset_request use EXTI_RPR and EXTI_FPR if present instead of EXTI_PR.
This is less precise than offered by the RPR/FPR registers, but makes
for a consistent experience in the common API.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
EXTICR on stm32g0 is in exti registers range. Previous chips used to have that
gpio port exti mux configuration accessible via AFIO_EXTICR or SYSCFG_EXTICR.
Also, the new chip now use 8 bits coded value instead of previously 4 for the
extcr mux selection value (see AFIO/SYSCFG/EXTI_EXTICR_FIELDSIZE)
Let's define two helpers: EXTICR_SELECTION_REG (to get proper AFIO/SYSCFG/
EXTI_EXTICR register) and EXTICR_SELECTION_FIELDSIZE (to get proper AFIO/SYSCFG/
EXTI_EXTICR_FIELDSIZE value), and use it them exti_select_source to determine
exticr mux selection bits shift and mask.
While on all current chips, exticr gpio port mux selection is coded on 4 bits,
stm32g0 EXTI_EXTICR register uses 8 bits. Align all exti header to reference
that value (was previously defined for f0 as SYCFG_EXTICR_SKIP)
flash_unlock_acr allows to unlock RUN_PD bit from FLASH_ACR register. Relock is done automatically
when writing 0 to RUN_PD, so no flash_lock_acr method.
Ettore Zaffaroni