10b63667b5
jenkins: publish github status always first
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need a result first, before we (potentially fail) to publish tests
2020-09-27 13:44:38 +00:00
b8461da137
jenkins: attempt to mark commit status only within libopencm3
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trying to get pr checks tto flag properly
2020-09-27 13:34:37 +00:00
09bf6e9ebc
jenkins: fix typo
2020-09-26 21:48:51 +00:00
11d2408289
jenkins: try and set commit status on correct commit
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Logs on jenkins showed it trying to set the commit state on the wrong
commits, the master of upstream, instead of the head of the PR
2020-09-26 21:41:12 +00:00
52dc1ff6d7
Update jenkinsfile after testing by edits live on jenkins
2020-09-10 21:19:55 +00:00
04dd4c6fc8
try out other ways..
2020-09-10 21:19:55 +00:00
3416f55ee9
jenkins hatr
2020-09-10 21:19:55 +00:00
d220e1daf6
fix syntax in jenkinsfile
2020-09-10 21:19:55 +00:00
efc4f08267
tests: gadget0-f3: allow custom local stlink
2020-09-10 21:19:55 +00:00
96953eeab3
draft jenkins file
2020-09-10 21:19:55 +00:00
bcd162c49a
trya nd make directories per
2020-09-10 21:19:55 +00:00
5275a1761f
hacky hacks
2020-09-10 21:19:55 +00:00
0bb9d882cc
tests: gadget-zero: add xunit reporting
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This is intended to help produce CI reporting on PRs and regression
testing.
2020-09-10 21:19:55 +00:00
24bef9c49e
stm32:adc: Change bitwise AND to logical AND
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The original bitwise AND was _functionally_ correct because all operands
were booleans, but it was very poor at conveying the intent.
Fixes #1230
2020-07-03 12:27:44 +00:00
90753950bb
stm32f3: Enable support for GPIO ports G and H
2020-04-30 08:29:08 +01:00
07bd38b814
stm32f3: Add GPIO ports G and H to memory map
2020-04-30 08:29:06 +01:00
e2299f14f2
devices.data: add stm32g030x6 and x8 chips
2020-04-24 10:25:33 +02:00
2ce5cc58ce
STM32F4: Add FMPI2C1 Peripheral to the memory map
2020-04-15 12:07:48 +00:00
3ee9710f35
STM32F4: I2C Noise Filter Register
2020-04-15 12:07:45 +00:00
503cebab87
stm32g4: turn on FPU in pre_main
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Yep, all M4F need this file added.
2020-04-10 14:12:08 +00:00
418b609230
devices.data: stm32g4: _actually_ finish adding
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Missed the CCM, missed the chain heads for the family itself.
2020-04-10 13:44:04 +00:00
9bf6ce8b64
stm32g0: flash: add erase/program stuff
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probably can be refactored with other chips, did not really looked yet.
2020-04-09 23:37:38 +00:00
dc98e2e6d9
stm32g0: flash: fix flash keys.
2020-04-09 23:37:38 +00:00
7cb7d51273
stm32g0: flash: update registers documentation
2020-04-09 23:37:38 +00:00
d696e2c264
stm32g0: add device electronic signature offsets and build desig.
2020-04-09 23:37:38 +00:00
2d9c01867f
stm32g0: update sysconfig based on latest stm32g0x1 RM
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add pin clamping diode control, available on g041 and g031
2020-04-09 23:37:38 +00:00
4e70d06d63
stm32g4: Add basic support
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* memorymap
* vectors
* rcc
* gpios
* makefiles
* devices for linker script generation
* doc structure
2020-04-09 23:29:00 +00:00
57373b3413
stm32l4: rcc: fix bit error in BDCR
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And add the new bit from later ref manuals
2020-04-09 22:04:49 +00:00
89e90e0e5d
pac55xx: gpio: fix gpio_set_af for pin alternate function settings.
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register bits were not cleared before setting. refactored to be similar
to how the drive strength register is being set.
2020-04-09 14:17:27 +00:00
abc74fd78b
stm32g0: fix typos in rcc.h
2020-04-08 07:50:14 +02:00
f4ec5b9f9b
stm32g0: fix RCC enums for UCPD peripherals
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The order of the UCPD1 and UCPD2 bits as described by the
rcc_periph_clken and rcc_periph_rst enums is swapped with regard to the
datasheet. Swap them.
2020-04-07 21:37:22 +02:00
b1d8a4c546
stm32h7: added minimal stm32h7 exti defs, which share with G0.
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Separated definitions that did not seem consistent between the "v2" EXTI
platforms. Added SYSCFG defs needed for EXTICR settings.
2020-03-23 09:23:21 -04:00
89074d6a13
stm32h7: fix inverted VOS settings for Vcore.
2020-03-10 10:16:26 +00:00
4a11e354a3
stm32l1: desig: use new mechanism to support different densities
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Fixes: https://github.com/libopencm3/libopencm3/issues/234
uses the new mechanisms introduced to address a similar problem on F7.
Tested on a medium density part (0x429) that returns the same ids as
before, tested on a high density part that now _doesnt_, but that's now
correct :)
2020-03-06 22:53:03 +00:00
78c23ba5a0
doc: stm32f4: fix broken groupings
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Now all the register value sets are in the generated output
2020-03-06 01:14:44 +00:00
b146fd6aa7
doc: stm32: flash: tidy up doxygen warnings and broken groupings
2020-03-06 01:14:17 +00:00
3df3ed7db9
doc: stm32f0/f3: adc: fix doxygen warnings
2020-03-06 01:13:22 +00:00
dca79bfd7a
doc: stm32l1: lcd: fix groupings and convert to doxygen
2020-03-06 01:11:45 +00:00
341bd84cb9
doc: stm32h7: cleanup warnings and groupings
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Move shifts and masks outside groups to clarify docs from a user point
of view. fix missing or broken groupings
2020-03-06 01:10:20 +00:00
4953d67aaa
stm32h7: per comments, improved consistency with other rcc impls.
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Reduced the sea of enums, and renamed config parameters to match other
implementations, cribbing off of the G0 config, as it is closer to the level
of complexity. Updated initialization code to utilize the new values.
Added flash and LDO configuration from RCC init to be more consistent with
STM32 platform initialization.
2020-03-05 22:07:10 +00:00
5f8cbb95e6
stm32: ltdc: clarify warning on faulty include
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No code change.
2020-03-05 21:59:29 +00:00
fb0cac49cb
stm32: adc-v2: add adc_{en,dis}able_delayed_conversion_mode
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To control AUTODELAY feature of the ADC.
2020-03-04 23:29:31 +00:00
f1073e7991
stm32h7: stop attempting to use common usart code.
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Until h7 implements a method of providing the periph clocks in a
compatible manner, they simply can't use the common_all files.
2020-03-04 23:24:02 +00:00
2ca56f4c21
stm32h7: updates to PWR and RCC to support PLL configuration.
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PLL configuration on the H7 is pretty involved, and takes a number of
configurations to make it work. In order to make peripheral drivers a bit
easier to implement, working with a soft clock tree in the rcc module which
stores the clock settings for each clock as they are setup such that users
can request the clock value from the RCC module for configuration. Added
getter for the clock which allows the user to pass the base address of the
peripheral, and get the peripheral clock value for convenience.
Clock configuration is still missing values for setting up all of the kernel
clocks for the peripherals, but this is in work, and there is a framework to
do so.
Have tested to 400MHz without issue. Peripherals that are explicitly supported
are working and the clock tree values appear to follow correctly.
Added LDO settings to allow setting the scaling to support high frequencies.
2020-03-04 23:17:02 +00:00
97688b913e
stm32: desig: refactor to allow targets to have different addresses
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In this commit, support for the different base addresses for different
F7 parts is added, but the mechanism is now in place for L1 and others.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
(whitespace fixed, commit msg reworded)
2020-03-04 22:16:31 +00:00
f1b4a4dfff
stm32f3: adc: consistently use unshifted
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and tweak teh docs a little
2020-03-04 22:02:45 +00:00
49285ed8e1
stm32f3: fix missing reg mask for adc_set_multi_mode
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Missing defines for ADC_CCR DUAL values have also been added.
2020-02-19 00:13:00 +01:00
cb0661f81d
stm32h7: fmc: added bit defs for async configuration.
2020-02-16 13:52:04 +00:00
72274d3caf
Remove SRCLIBDIR definition from the top Makefile
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All submakefiles have sensible defaults (either .. or ../..), so there is no need to fiddle with whitespaces in the dir name.
2020-02-02 10:55:01 +00:00
sur5r
d0d23cff07
ld: lpc17xx: Fix RAM2_OFF on LPC17[78]x
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- RAM2_OFF is at 0x20004000 (see UM10470 page 15)
- 0x20040000 is not a valid address on LPC17[78]x
2020-01-31 20:52:12 +00:00
Karl Palsson
sur5r