Turns out, there's lots of common code for flash. Pull up prefetch
on/off to start with, as there's only a single bit name different.
Pull up the definitions of common API functions too, starting with
flash_set_ws. Even if the implementations are different, things that
meant to be the same, should be defined centrally.
- Change .power_save to .voltage_scale, a pwr_vos_scale enum
- Enable pwr clock before setting VOS scale
- Fix flash wait states
- Make flash_set_ws more robust
According to: https://gcc.gnu.org/onlinedocs/gcc-6.2.0/gcc/ARM-Function-Attributes.html
"Only basic asm statements can safely be included in naked functions (see Basic
Asm). While using extended asm or a mixture of basic asm and C code may appear
to work, they cannot be depended upon to work reliably and are not supported."
The LTDC include file was defined with combined bit
semantics and bit position. As a result instead of
LTDC_GCR_VSPOL which is the bit which defines vertical
sync polarity, this had been defined to be
LTDC_GCR_VSPOL_LOW (0) and LTDC_GCR_VSPOL_HIGH (non zero).
This sort of define makes it impossible to know ahead of
time what operation would set or reset the bit (some are
negative logic, others are postive logic, so affirmative
defines could mean either "set the bit" or "reset the bit"
I've added the non-semantic bit define so that it is clear
in my code if the bit is being set or reset.
Discussion took place at https://github.com/libopencm3/libopencm3/pull/889
We didn't actually mark it deprecated very well, but it was
non-functional, and simply a poorly implemented wrapper for
rcc_periph_reset_pulse() anyway.
It's now been obsoleted in the examples for more than a year, and it's
time to kill it outright.
Fixes: https://github.com/libopencm3/libopencm3/issues/709
Only applied to STM32 doc trees at present.
Instead of declaring a group for "STM32blah" in the doc-blah.h files,
and then trying to put all the common+specific peripheral code into
those groups, (which is what led to the stub doxygen holder empty .c
files) Just use a standard name like "Peripheral APIS" and place
everything into that.
Demonstrated by converting ADC and USART peripherals, which is
definitely not complete, but it shows how to make things less magical,
and less prone to copy/paste errors. Now, you can copy/paste and it
will do the right thing, because everyone uses the same group names.
This is also how to unify the mix of "STM32blah->Periphblah" and _also_
the dangling "periph_file" modules in doxygen, it merges them together
properly, as they're intended to be really.
Deprecate the old routine and make a new one that actually handles HSI
and HSE properly, and includes the predivider and the usb divider
settings as well.
STM32L0 uses the same DMA peripheral as STM32F0, F1, L1 and others
with some differences. Those are mostly in the number of supported
controllers and channels.
This patch enables the basic support with no attempt to only expose
the available controllers / channels.
For more information see the ST Application Note AN2548.
Signed-off-by: Martin Sivak <mars@montik.net>
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
Somewhat replaces some earlier work done by hg/lg, but much more
complete, so we kept it as is, because it's bringing in even more parts
after this.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Applies to both, and clearly shows that cmu.h needs to be extracted as
common code.
Originally from: e31d312331
and checked in the HG/LG reference manuals.
The original submitter of this squished everything into one series, and
has not returned. The code mostly appears good, and review comments were
followed for the most part. The project doesn't really maintain any
testing or board farm for sam3/sam4 parts, so we're going to just trust
our users.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
sam/4l: IRQ Configuration file (irq.json)
sam/4l: Basic Memory Map.
sam/4l: GPIO Defines.
sam/4l: GPIO Functions
Added everything that needed to compile the library: Makefile, Linker
Script and common includes.
sam/4l: SCIF function to start OSC.
sam/4l: GPIO Enable/Disable and Multiplexing configuration functions.
sam/4l: PLL Clock configuration.
sam/4l: Peripheral clock configuration and basic USART support.
sam: USART Character length configuration.
sam/4l: Generic Clock configuration functions.
sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
Originally sourced from: https://github.com/libopencm3/libopencm3/pull/382
fixed some typos from the manual and poor merging/rebaseing,
and one judgment call on using a specific name for a conflicting
bit definition.
stm32f0, l3, l4 are currently sharing the same duplicated header, and
stm32l0 uses the same peripheral. Stop copy-pasting stuff and centralize
definitions into a iwdg_common_v2.h header.
The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips.
Rename the files to make this more clear, and easier to use in other
targets.
This _breaks_ your gpio code for F2 and F4. It makes them consistent
with the reference manual, and more consistent with all other families
and general expectations.
OLD code -> NEW code
RCC_AHB1RSTR_IOPxRST -> RCC_AHB1RSTR_GPIOxRST
RCC_AHB1ENR_IOPIxEN -> RCC_AHB1ENR_GPIOxEN
RCC_AHB1LPENR_IOPxLPEN -> RCC_AHB1LPENR_GPIOxLPEN
[We're not actually breaking it, see the next commit for deprecated
aliases]
Final chunk of register definitions to be pulled up.
Now the "target" files are _only_ defining the list of u(s)arts
available, and any _specific_ functions for that target.
Just small pieces at a time to make it easy to see what's happening.
Taking definitions currently implemented in both f0/f3 headers and
making combined, documented versions in the -v2 header.
Use the usart-common base plus the usart-v2 code, instead of private
implementations. Less code, more common apis across targets.
Of note is the trick to make F0 look like it has an APB2 bus. It's the
only stm32 that doesn't have a documented APB2 bus, but still has
peripherals enabled via an "APB2" register, and they match how other
targets have an APB2. Simply make APB2 an alias of APB1, as it's only
used for clock speed detection.
Instead of declaring that _every_ device has USART1,2,3 and UART4,5, let
the targets themselves define what periphs they do, along with their
USARTx_BASE defines, and let the common headers just have the common
abstractions.
Similar to how we have abstract defines for the stop bits, parity and
flow control common mode namees, provide abstract flag names for the
"standard" flags. This allows us to start using common API code for v1
and v2 uarts
For stm32f3, drop the "compatibility" defines that simply pollute the
namespace, making it confusingly appear as if f3 has both SR and ISR
registers.
Only pulling out the _common_ stuff. This is a single step in a long
process of eliminating all the duplication and "same, but different"
implementations that are stalling adding nice clean easy support for
l0/f7/l4.
This _ignores_ all currently conflict register definitions, even if they
"do the same thing" it just pulls up the common stuff. A subsequent
commit can look at resolving the implementatations to a single version.
Added the CAN1 compatibility aliases as has been done for adc and dac to
make code reuse easier. Only for the magic enums, the raw bit
definitions remain as per the ref mans
Originally suggested as https://github.com/libopencm3/libopencm3/pull/802
the RCC_TIM17 and RCC_TIM18 macros used in the "new" style were ok, just
the old style raw bit definitions.
Reported-by: Karl Hammar <karl@aspodata.se>
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
Originally suggested in https://github.com/libopencm3/libopencm3/pull/399
At least provide macros for each family that allows easy masking of the
full set of reset reason flags. Trying to provide a function that
provides these in random upper bits seems unclear at best.
Reserved bits are marked explicitly in the comments. ASCR defines
are changed to be consistent with the reference manual. HYSCR,
ASMR, CMR and CICR register defines are rewritten to be more
concise and readable.
For both v1 and v2, provide routines to help do arbitrary length
write/read transfers.
Tested with multiple byte writes and reads, for both 100khz and 400khz,
with repeated starts and stop/starts. However, only tested (presently)
with a single i2c target device, a Sensiron SHT21 sensor. Extended
testing against eeproms and alternative devices would be useful
If you're interested in slightly underclocking or midrange speeds,
you're into custom environments. Drop all the "helpers" for these odd
speeds. This is not the max speed for any existing f0 part.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
The following four new functions enable clocking SoC from HSE crystal:
rcc_clock_setup_in_hse_8mhz_out_{8,16,32,48}mhz
These functions start HSE as external clock and feed its output to PLL
if higher frequency is needed.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
-> Dropped 8,16,32Mhz functions as superfluous.
Early revisions of the reference manuals used different names for the
touch sense controller and firewall bits. These have now been changed
to be more in line with other families, and as these parts and bits were
new in this library, simply move forward to the current naming
convention.
According to reference manuals both l0 and l4 have "v2" i2c peripheral.
This patch adds i2c support to l0 and l4 using previously unified "v2" i2c
headers and implementation.
No real hardware has been tested so far. Only compilation tests for both
libopencm3 and libopencm3-examples for all stm32 families.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
The f1, f2, f4, l1 chip families have a similar "v1" i2c peripheral on board.
More recent f0, f3, l0, l3 chip families share another "v2" version of i2c.
This patch unifies headers and implementation for two types of i2c peripherals:
- rename: i2c_common_all.[ch] to i2c_common_v1.[ch]
- remove i2c_common_f24.h: extra I2C blocks are defined in specific headers
- use f3 i2c code as a basis for common "v2" i2c implementation
- add f0 i2c support: use "v2" i2c implementation
Tests:
- tested on a custom f0 board
- compile-tested both libopencm3 and libopencm3-examples for all stm32
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Add three more RTC clock helper functions:
- rcc_set_rtc_clock_source
RTC on stm32/f0 can be clocked from the following three
sources: LSI, LSE (32.768Hz), HSE/32.
- rcc_enable_rtc_clock
- rcc_disable_rtc_clock
enable/disable clocking RTC module using selected clock source
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Add clock config for the 25MHz crystal found on the discovery board.
Verified to work on the STM32F7-Disco.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Modified namespaces and types->structs to avoid namespace pollution as
was fixed for other families in:
3a7cbec7: stm32l/stm32f: name space standardization [BREAKING]
It was never complete, even for F1 family code, and went on to be even
less complete for f0 and f3. The usefulness of a library function to
check for both the irq being enabled _and_ the status flag is highly
questionable, and caused known user confusion.
The existing, much simpler, and fully functional usart_get_flag() is
a good replacement in almost all sane use cases.
Fixes https://github.com/libopencm3/libopencm3/issues/734
Simplified blocking API, with an async routine if you really need it.
Follows as best as I can understand the reference manual, but testing
those conditions will be difficult.
SHCSR and DFSR are only implement on ARMv6 if the "Debug extension" is
implemented, but that's pretty much everywhere, so allow access to the
defines.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Some parts used HSICLK, some used HSI. Most used NOCLK, f3 used
DISABLED. Try and move all to the shorter, simpler forms, instead of
having mixed defines for different targets for the same thing. Just
because the bits themselves are different doesn't mean we should make it
more difficult for users to port code.
MCOPRE prescaler definitions used a _SHIFT and a preshiftd definition.
The rest of the file uses separate _MASK and _SHIFT definitions.
Fix whitespace on the definitions while we're here.
The f107 ethernet peripheral is the same as in f4, and was pulled out
into lib/ethernet/mac_stm32fxx7.c in 52758bb8fd
This drops the duplicate code.
Fixes Github issue #694
The TSVREFE bit is defined to only be present on ADC1, so drop the
pointless adc argument. This has the added benefit of making the
API consistent with all other STM32 adc parts.
Use same names as adv-v2 peripheral uses. F1 is the only v1 peripheral
adc that has calibration modes at all.
Old:
adc_calibration(ADC1); // blocking call
New (blocking):
adc_calibrate(ADC1);
New (asynch):
adc_calibrate_async(ADC1);
// do stuff
adc_is_calibrating(ADC1); // false when calibration finished
Old routines are preserved but marked deprecated for now.
Extract the calibration code from the f0, and share it with the other
adc-v2 peripheral users (f0,l0,f3,l4)
Uses the same naming set of is/async naming conventions requested by the
RTOS guys instead of having blocking only calls.
Old code:
adc_calibrate_start(ADC);
adc_calibrate_wait_finish(ADC);
New code (blocking):
adc_calibrate(ADC);
New code (asynch):
adc_calibrate_async(ADC);
// do stuff
adc_is_calibrating(ADC); // will be false when it's finished.
Old code for f0 is still available, but marked deprecated.
Start providing async routines for all blocking routines, to make it
easier to use libopencm3 in some RTOS environments. This is not in
anyway intended to be complete, this just covers a single blocking
routine, rcc_wait_for_osc_ready. Documentation added to the top level,
and provided for all stm32 families.
Thoughts: should this be a "sam0" family rather than samd? (Much like Atmel's
own software package lumps all the cortex-m0+ devices in one family)
This was enough to get a basic blinky working at least.
This is common code for f0234, keep renaming files as has become standard, even
if it's a suboptimal solution. This doesn't rename the header which was not
renamed for f3.
Reported-by: https://github.com/gtoonstra
Original implementation only checked whether the user had _selected_ the
clock, not whether it had actually switched to the clock or not. For
almost all cases, this made this function either a no-op, if you _had_
selected the clock, or a blocking loop if you hadn't selected it ahead
of time.
Fixes github issue #687
This was inspired by an Arch Linux provided ARM GCC 5.3.0 bug:
It gave an
"internal compiler error: in expand_expr_addr_expr_1, at expr.c:7736"
with the array version of the desig_get_unique_id.
While I was at it, fixed:
- a potential alignment issue with casting uint8_t* buf to uint32_t*
- a funny static in the string definition that does nothing (given const)
This reverts commit aa5e108553.
This commit was not meant to land yet, it should have gone for review, and
doesn't yet include all the parts it should touch.
replace bulky hardcoded wait for set and wait for clear with a single asynch
routine. Leave the blocking routines in for compatibility at this point.
NOUP: should be added to other rcc.c files too.
L4 and F3 actually have the same bits to write in the same order, but F3 hides
the name of the deep power down bit. Keep the like that for now, but there's a
standard API for enabling and disabling the regulator.
Now that the big pieces of the adc-v2 common files are in place, start
including l0 in the builds. This includes only the very very basic core v2
peripheral functions, and the very basic definitions.
The adc v2 periph has the same register map, but comes in two flavours, one
supporting injected channels, more watchdogs, per channel sampling times and
so on, and one "simple" version.
Pull up the f3 and f0 portions into the appropriate files, after comparing with
L0 and L4 reference manuals, even if those are not fully landed yet.
The f0, f30x and l0 have a very similar "v2" adc peripheral.
Start extracting out some of the common code, and fix the glaring bug in
adc_power_down that was affecting them both.
This is not intended to be a fully comprehensive extraction, just the first
easy steps.
The adc peripheral on F30x is the same as F0, L0 and L4. In the reference
manuals, the following names are used.
F3: CFGR (no CFGR2)
F0 and L0: CFGR1 and CFGR2
L4: CFGR and CFGR2
Moving to a single consistent name, that's more likely to be inline with future
part numbers makes it much easier to extract common driver code for the
peripheral.
While all bit defines are moved to the CFGR1 style, core register definitions:
ADC_CFGR(adc) and ADCx_CFGR are kept to match the original register name in the
reference manual.
Fixes Github issue #548
There are as many SMPRx registers are needed for channels supported, and on all
other families, the field definitions are just ADC_SMPR_SMP_XXX. For
consistency, and to avoid any confusion or duplication, use the same style here
too. Drop silly unused per channel definitions that have no purpose.
At least temp sensor, vrefint and vbat/vlcd should have consistent names and
consistent doxygen.
Dropped channel definitions that are the same as the raw number.
It's not used anywhere, and if this sort of api becomes needed, it can be
designed cleanly and finished.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This is more in line with the actual hardware (u32 registers), and will still
work if PRIMASK or FAULTMASK ever have more than 1 bit defined.
The functions cm_is_masked_interrupts() and cm_is_masked_faults() are
unchanged, since returning 'bool' fits with the function naming.
Fixes most of github issue #475. What remains "unfixed" is the absence
of functions to simply 'get' the u32 value of PRIMASK and FAULTMASK registers.
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly
and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM)
Remove the duplicate here.
The MPU RASR Shareable, Bufferable and Cacheable bits are all individual
bits, and none of the existing defines appear to even match the ARM
documentation. Remove them, but leave the definitions of the bit
positions.
Reported by MightyPork on IRC
Original commits, while appearing clean and tidy, hadn't even been
compile tested. Trust no-one. Not even Scully.
Fixes: 770878e7b4
Fixes: 86d20ef00c
Fixes: 05ff0df322
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation:
-multiple calls to cm_is_masked_interrupts() in the same scope/context
- -Os or -O2 optimization
This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts().
Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
These prototypes affect functions defined by application code. Only
the implementations in libopencm3 are supposed to be weak; the
functions in application code should definitely not be. Otherwise,
you'll end up with two weak symbols being linked together, and
it's luck as to which one the linker picks.
Just the basic core common functionality gained for free by being a common
peripheral. Enough for a miniblink.
Fixes some errors in the GPIO memory map. ST's naming of AHB2 vs AHB3 is
confusing.
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.
Only stub support so far, but this opens up the beginning of build testing.
Many stm32 families have multiple ADC and DAC peripherals. F0 (so far) only
has one. To make it easier to use the same code on many stm32 families,
provide an alias for ADC1 to ADC.
After adding support to the f3, add missing doxygen support to the f0
equivalent. This improves things and keeps them consistent until/if they are
pulled out as common code.
Based on the f0 support, which has identical functionality, but with doxygen
added. Bits renamed as they are only HSE prediv on some targets, and makes
things more consistent with the f0.
Fixes part of github issue #560
This function was badly copied and pasted from the f4 library, where there are
two functions, rcc_set_main_pll_hsi and rcc_set_main_pll_hse which combine
source, multipliers, dividers and other pll factors.
On F3, (not all of them, but the ones we support now), the function as
implemented has nothing to do with hsi / hse, and instead is simply selecting
the PLL multiplier.
Copypasta from f4 rcc code was only modified to shift the result, but not clear
the existing settings properly. Add mask/shift definitions and use them
properly.
TSC_IOGxCR is actually a 32 bit register, of which 13 bits are used
(rest are reserved).
Also, added x-1 since G0 is not a valid group, TSC_IOGCSR_GxE(1) is supposed
to be at 0x34, not 0x38.
Was only in the (obviously out of date) documented example and as a
declaration. No implementations. Dropping immediately, but documentation
still needs further work.
Most changes are noise from doxygen.
Readme udpated to explain newer FP_FLAGS for m7
stm32f7 library is skipped if the toolchain doesn't support it yet.
GUSBCFG TRDT fields have very particular meanings, and the field should be set
depending on your bus speed. There's no 8/16bit meaning in any current
reference manual for this field.
Fixes github issue #530
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
More could probably be found, but this makes some of the basic RCC defines for
the L0 much more inline with other platforms, and much less verbose. This
helps us have more identical code for library users across different targets.
Based on previous work, add a new driver for the v2 usb peripheral found on
stm32f0 and l0 devices.
Correspondingly, add a usb gadget zero test suite for the f0. L0 device level
code isn't yet ready, but will add the test case when it moves in.
Work by Frantisek Burian, Kuldeep
Singh Dhaka, Robin Kreis, fenugrec and zyp on irc, and all those forgotten.
The breaking changes here changes in header location, and changes in driver
name passed down to the usb stack.
Changes affect: stm32f102/f103, stm32l1, and some f3 parts
* instead of the confusingly generic "usb" use the name "st_usbfs" for the USB
Full speed peripheral ST provides in a variety of their stm32 products.
Include directives should change as:
#include <libopencm3/stm32/usb.h> => <libopencm3/stm32/st_usbfs.h>
* instead of the confusingly specific "f103" name for the driver, use
"st_usbfs_v1" [BREAKING_CHANGE]
Instead of:
usbd_init(&stm32f103_usb_driver, .....) ==>
usbd_init(&st_usbfs_v1_usb_driver, .....) ==>
The purpose of these changes is to reduce some confusion around naming, but
primarily to prepare for the "v2" peripheral available on stm32f0/l0 and some
f3 devices.
Work by Frantisek Burian, Kuldeep Singh Dhaka, Robin Kreis, fenugrec and zyp
on irc, and all those forgotten.
* USB host register definitions added.
* Extracted common register and bitfield definitions
from 'otg_fs.h' and 'otg_hs.h'
into new file 'otg_common.h'.
Modified usb low-level drivers to adopt to new style of bitfields.
* Fixed typo OTG_GOTGIN -> OTG_GOTGINT (according to the datasheet)
Signed-off-by: Amir Hammad <amir.hammad@hotmail.com>
The MPU is an implementation option available for both ARMv6-M and ARMv7-M.
Remove poorly merged code that attempted to include this only for cortex m0+.
Added doxygen, updated the definitions of the RBAR register, (though if you're
really using this periperhal, you should be looking at the ref man for further
information)
Reported-by: forrestv on irc.
All STM32 family pwr.h must use LIBOPENCM3_PWR_H as include guard so that
pwr_common.h can detect that it has been referenced by pwr.h for
each family. F2 and F3 had the wrong include guard.
Fixes Github issue #513
This removes the shift from the defines, and includes them in the helper
function, making the code match the documentation, and following how the
rest of the library commonly operates.
Code using the existing defines will continue to work.
Basic helpers to at least support common configurations for the f401.
Original submission specified 5 wait states, but the reference manual and other
reviewers all believe that 2ws is sufficient for these modes.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This makes it easier to read for most people, and makes it substantially
easier to review changes in the function signatures themselves at a
later date.
The f3 adc has separate bits for end of conversion and end of sequence.
Support those fully, with the regular enable/disable irq methods, and
the flag checking methods.
Discovered in github bug: #493
This code was copied from the f4, and blindly modified to make it seem
to work. The f3 has separate flags for EOC and EOS, it doesn't use a
second bit to configure what the EOC bit does.
Consequently, update the documentation to correctly indicate that the
EOC bits are only set per conversion.
Discovered in github bug: #493
While there might be other places that are missing this include, this
particular file is clearly missing them, and has resulted in a few separate bug
reports. Fix it right now, in the name of continuous improvement.
Fixes#310 and #427
This adds MCO source selection to some targets, and removes and standardizes
the mask/shift usage for all targets. For devices that support MCO2, this
supports only MCO1. No attempt has been made to extract MCO prescaler, which
is not available on all F1 and F3.
This commit implements the support for one interface to have multiple
altsettings. It also adds hook that user can use to perform actions
when the alsetting switch is performed by host.
Changes:
* For backward compatibility, placed a pointer instead of allocating memory for whole interface struct.
* Always execute callback (even if the current interface alternate-settings matches).
* Multiple configuration support.
Signed-off-by: Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
When writing the USB endpoint register, USB_EP_RX_CTR (bit 15) and
USB_EP_TX_CTR (bit 7) should be set to avoid inadvertently clearing
either bit.
Prior to this patch end points could indefinately stall if the hardware
changed these bits between the time they are read and when they were
written.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Added CLR_REG_BIT_MSK_AND_SET and TOG_SET_REG_BIT_MSK_AND_SET because we
need version of CLR_REG_BIT_MSK and TOG_SET_REG_BIT_MSK that allow us to
OR in bits before the register is written.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Provides all of the config descriptors for MIDI class devices together
with a sub-set of the audio class sufficient to put together a full
fledged MIDI device.
Extends struct usb_endpoint_descriptor to make it possible to provide
the USB host with class-specific extensions to endpoint descriptors.
The approach taken, based on extra and extralen and removing the sizeof()
from USB_DT_ENDPOINT_SIZE, is identical to the approach used to add
class-specific extensions to interface descriptors. All libopencm3-examples
use the USB_DT_ENDPOINT_SIZE (rather than directly using sizeof) so there
should be no compatibility problems resulting from this change.
Rename rcc_ppre1_frequency and rcc_ppre2_frequency to rcc_apb1_frequency and rcc_apb2_frequency
Also add rcc_ahb_frequency (although it is not set correctly in all cases) which will be fixed by
the rcc commits later. Also fixup the only use in the library of these variables, the USART code.
And fix the typos that resulted
Make l1 generic too
Pulls out duplicate calls from f0/rcc.c and uses the common version which
also means that f0 can use rcc_peripheral_enable() now which is in common
but not the old rcc versions.
Tested with a miniblink example on the l053 discovery board.
Only register definitions at this stage, no helpers.
Register definitions from RM0367r2, hopefully the biggest
superset of L0 parts.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
F100 has more remap options than F10x, particularly on the High Density
devices.
Fixes github issue #365
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
The bits definitions for direct manipulation were missing, and should be
present for completeness. However, this only affects the legacy (error prone)
API, replaced some time ago.
old and error prone: (stop using code like this)
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM16EN);
rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM16RST);
new:
rcc_periph_clock_enable(RCC_TIM16);
rcc_periph_reset_{pulse,hold,release}(RCC_TIM16);
Fixes github issue #361
Add I/O mux controller which is required to mux pins according to
their used function. For all pads, the alternative function 0 is
GPIO. For different pin mux function refer to the reference manual.
This adds GPIO module support. GPIO can be controlled using the GPIO
number as stated in the reference manual, similar to Linux. Also
32-bit access to whole ports is possible. Reading a GPIO is possible
without muxing the pad as GPIO, however writing a GPIO needs the pad
to be muxed as GPIO.
This adds UART support for Vybrid VF6xx. Baud rate is calculated
from IPG clock, which need to be initialized by using the
ccm_calculate_clocks functions. Also clock need to be gated using
the ccm_clock_gate_enable function. Tested with an unitialized
UART with a baud rate of 115200.
Extend the clock controller module with a function to calculate
core clocks from the current registers settings. On Vybrid, we
assume that the core clocks are setup by the main operating system
running on the Cortex-A5. Nevertheless we need to know their actual
values in order to calculate other clocks or baud rates.
Verified on a Colibri VF61, which calculates following values:
ccm_core_clk: 500210526
ccm_platform_bus_clk: 166736842
ccm_ipg_bus_clk: 83368421
Add initial memorymap for Vybrid VF6xx module. Also add the clock
control module which allows to control system clocks and enable
clocks of individual pheripherials.
Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models
have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds
initial support for the Cortex-M4 in the libopencm3 library.
By using two different ram areas (pc_ram and ps_ram) the user can
put the code in a RAM area bounded to the code bus. The data can
be stored in the data area. However, currently the initial values
of for the variables in the data section are stored in the code
section and copied to the ram section by the initialization code
(like it's copied from ROM to RAM on microcontrollers).
Latest versions of all reference manuals refer to the address as SPIx_BASE, and
simply name some of the individual registers as SPI_I2SXXXX. Likewise, the
interrupts are simply SPIx, not SPIx/I2Sx. Rather than hacking more duplicates
into the F0 and L0 parts where this was turning up, remove the pointless _I2S_
from SPI2/SPI3 and make it all consistent
Compile tested only, with the examples collection.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Fixes#331Fixes#347
There's more exti lines on many more devices now. F0 and F3 have extras, as did
L1 and L0. There's no real reason not to have higher order EXTI definitions
defined at the top level, and it reduces the number of files to merge together
to find all definitions for the bigger devices.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Fixes#338
Karl Palsson