the group defaults to the implicit container based on location, so drop
all the explicit @ingroups, less to maintain. Properly use /**@}*/ to
close all groups too, even though it mostly seems to have worked anyway.
Properly close all groups opened for files.
Make the names match the reference manuals properly, and add missing
names. Still a long way to go to unify across all families, but this is
at least closer.
here, it's a bit of a mess.. G0 flash controller does not really
match exsting feature split. IE it has instruction cache only ..
so, no flash_idcache.c as it. flash_common_f could be used, but
flash_unlock would not take care of option byte ?
prefetch, icache and lock is ok. I had no look at flash programming
or erase yet..
While this appears to be a backward change, this moves the _register_
definitions (their addresses) and the actually specific to f4/f7
numbering back into the explicit headers. Potentially this could be
pulled out again, but it's not much code.
This then allows the stm32l1 to use all the rest of this code, with the
differences really being just the addresses of the registers.
Never seen any reason for these noisy verbose defines. They're not
helpful, and we've never needed them for doing sequence setting code
anyway. Just drop them.
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.
Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.
From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage. We can
see where they move in the future.
While on all current chips, exticr gpio port mux selection is coded on 4 bits,
stm32g0 EXTI_EXTICR register uses 8 bits. Align all exti header to reference
that value (was previously defined for f0 as SYCFG_EXTICR_SKIP)
flash_unlock_acr allows to unlock RUN_PD bit from FLASH_ACR register. Relock is done automatically
when writing 0 to RUN_PD, so no flash_lock_acr method.
It's always stream on the "new" dma controller (unless it's channel....)
Fix a couple of inconsistent prototypes that had carried over from f1
originally. Reported by vampi on irc.
usb_disconnect() is board/platform specific for chips that don't have
built-in handling for this. Allow the application to provide its own
version of usb_disconnect() to handle this.
See https://github.com/libopencm3/libopencm3/pull/924
I2C3 is on many parts, but wasn't properly supported with the register
definitions. Declare them centrally, just depending on the memorymap
defining them. On some parts, the rcc bits were defined, but not the
base registers.
Fixes: https://github.com/libopencm3/libopencm3/issues/820
Just a small typo I came across while trying to get MCO to work on my board.
The define is not used in any other files as far as I can tell, but of
course applications might break if they use the misspelt variant.
flash_clear_pgperr_flag is a name used on f247, which is actually most
analogous to the SIZERR bit on l4, (it's a parallelism error)
the bit being cleared originally in this function, PROGERR is a new bit,
and should have it's own name.
Add a function to handle the previously unhandled size/parallelism flag,
and rename the existing one to properly reflect it's new name.
This shows what is _actually_ different for f7. A couple of option
bits, and a renaming of bit 7 of the status register, from Program
Sequence Error to Erase Sequence Error.
We keep the separate implementation of wait_for_last_operation, to meet
the "suggestions" of the reference manual to insert a DSB instruction.
Keeping the renamed bit/functions also requires us to keep separate
implementations of the flag clearing functions
Move the last few register defines back to their relevant headers, add
doxygen and groups. While these registers _were_ "common" they were the
_only_ common things, so it's simpler for future work (merging f7 with
f2/4) to move them back separately.
F3's flash interface is actually quite different, don't try and force
sharing code that isn't really related. The "PGERR" is a very different
bit than the parallelism error that f2/4/7 have.
l4 is pages, not sectors, so update apis to be consistent. (other
families use page/sector as defined in the reference manual)
Make sure that pages on the second bank can also be erased. Use the
same style in use for f2/4/7 for sector numbers across banks.
All the "f" type flash parts have an EOP flag, even if it's in different
bit positions. Add a header for this common functionality, and move
it's implementation to the existing common file.
Turns out, there's lots of common code for flash. Pull up prefetch
on/off to start with, as there's only a single bit name different.
Pull up the definitions of common API functions too, starting with
flash_set_ws. Even if the implementations are different, things that
meant to be the same, should be defined centrally.
- Change .power_save to .voltage_scale, a pwr_vos_scale enum
- Enable pwr clock before setting VOS scale
- Fix flash wait states
- Make flash_set_ws more robust
According to: https://gcc.gnu.org/onlinedocs/gcc-6.2.0/gcc/ARM-Function-Attributes.html
"Only basic asm statements can safely be included in naked functions (see Basic
Asm). While using extended asm or a mixture of basic asm and C code may appear
to work, they cannot be depended upon to work reliably and are not supported."
The LTDC include file was defined with combined bit
semantics and bit position. As a result instead of
LTDC_GCR_VSPOL which is the bit which defines vertical
sync polarity, this had been defined to be
LTDC_GCR_VSPOL_LOW (0) and LTDC_GCR_VSPOL_HIGH (non zero).
This sort of define makes it impossible to know ahead of
time what operation would set or reset the bit (some are
negative logic, others are postive logic, so affirmative
defines could mean either "set the bit" or "reset the bit"
I've added the non-semantic bit define so that it is clear
in my code if the bit is being set or reset.
Discussion took place at https://github.com/libopencm3/libopencm3/pull/889
We didn't actually mark it deprecated very well, but it was
non-functional, and simply a poorly implemented wrapper for
rcc_periph_reset_pulse() anyway.
It's now been obsoleted in the examples for more than a year, and it's
time to kill it outright.
Fixes: https://github.com/libopencm3/libopencm3/issues/709
Only applied to STM32 doc trees at present.
Instead of declaring a group for "STM32blah" in the doc-blah.h files,
and then trying to put all the common+specific peripheral code into
those groups, (which is what led to the stub doxygen holder empty .c
files) Just use a standard name like "Peripheral APIS" and place
everything into that.
Demonstrated by converting ADC and USART peripherals, which is
definitely not complete, but it shows how to make things less magical,
and less prone to copy/paste errors. Now, you can copy/paste and it
will do the right thing, because everyone uses the same group names.
This is also how to unify the mix of "STM32blah->Periphblah" and _also_
the dangling "periph_file" modules in doxygen, it merges them together
properly, as they're intended to be really.
Deprecate the old routine and make a new one that actually handles HSI
and HSE properly, and includes the predivider and the usb divider
settings as well.
STM32L0 uses the same DMA peripheral as STM32F0, F1, L1 and others
with some differences. Those are mostly in the number of supported
controllers and channels.
This patch enables the basic support with no attempt to only expose
the available controllers / channels.
For more information see the ST Application Note AN2548.
Signed-off-by: Martin Sivak <mars@montik.net>
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
Somewhat replaces some earlier work done by hg/lg, but much more
complete, so we kept it as is, because it's bringing in even more parts
after this.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Applies to both, and clearly shows that cmu.h needs to be extracted as
common code.
Originally from: e31d312331
and checked in the HG/LG reference manuals.
The original submitter of this squished everything into one series, and
has not returned. The code mostly appears good, and review comments were
followed for the most part. The project doesn't really maintain any
testing or board farm for sam3/sam4 parts, so we're going to just trust
our users.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
sam/4l: IRQ Configuration file (irq.json)
sam/4l: Basic Memory Map.
sam/4l: GPIO Defines.
sam/4l: GPIO Functions
Added everything that needed to compile the library: Makefile, Linker
Script and common includes.
sam/4l: SCIF function to start OSC.
sam/4l: GPIO Enable/Disable and Multiplexing configuration functions.
sam/4l: PLL Clock configuration.
sam/4l: Peripheral clock configuration and basic USART support.
sam: USART Character length configuration.
sam/4l: Generic Clock configuration functions.
sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
Originally sourced from: https://github.com/libopencm3/libopencm3/pull/382
fixed some typos from the manual and poor merging/rebaseing,
and one judgment call on using a specific name for a conflicting
bit definition.
stm32f0, l3, l4 are currently sharing the same duplicated header, and
stm32l0 uses the same peripheral. Stop copy-pasting stuff and centralize
definitions into a iwdg_common_v2.h header.
The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips.
Rename the files to make this more clear, and easier to use in other
targets.
This _breaks_ your gpio code for F2 and F4. It makes them consistent
with the reference manual, and more consistent with all other families
and general expectations.
OLD code -> NEW code
RCC_AHB1RSTR_IOPxRST -> RCC_AHB1RSTR_GPIOxRST
RCC_AHB1ENR_IOPIxEN -> RCC_AHB1ENR_GPIOxEN
RCC_AHB1LPENR_IOPxLPEN -> RCC_AHB1LPENR_GPIOxLPEN
[We're not actually breaking it, see the next commit for deprecated
aliases]
Final chunk of register definitions to be pulled up.
Now the "target" files are _only_ defining the list of u(s)arts
available, and any _specific_ functions for that target.
Just small pieces at a time to make it easy to see what's happening.
Taking definitions currently implemented in both f0/f3 headers and
making combined, documented versions in the -v2 header.
Use the usart-common base plus the usart-v2 code, instead of private
implementations. Less code, more common apis across targets.
Of note is the trick to make F0 look like it has an APB2 bus. It's the
only stm32 that doesn't have a documented APB2 bus, but still has
peripherals enabled via an "APB2" register, and they match how other
targets have an APB2. Simply make APB2 an alias of APB1, as it's only
used for clock speed detection.
Instead of declaring that _every_ device has USART1,2,3 and UART4,5, let
the targets themselves define what periphs they do, along with their
USARTx_BASE defines, and let the common headers just have the common
abstractions.
Similar to how we have abstract defines for the stop bits, parity and
flow control common mode namees, provide abstract flag names for the
"standard" flags. This allows us to start using common API code for v1
and v2 uarts
For stm32f3, drop the "compatibility" defines that simply pollute the
namespace, making it confusingly appear as if f3 has both SR and ISR
registers.
Only pulling out the _common_ stuff. This is a single step in a long
process of eliminating all the duplication and "same, but different"
implementations that are stalling adding nice clean easy support for
l0/f7/l4.
This _ignores_ all currently conflict register definitions, even if they
"do the same thing" it just pulls up the common stuff. A subsequent
commit can look at resolving the implementatations to a single version.
Added the CAN1 compatibility aliases as has been done for adc and dac to
make code reuse easier. Only for the magic enums, the raw bit
definitions remain as per the ref mans
Originally suggested as https://github.com/libopencm3/libopencm3/pull/802
the RCC_TIM17 and RCC_TIM18 macros used in the "new" style were ok, just
the old style raw bit definitions.
Reported-by: Karl Hammar <karl@aspodata.se>
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
Originally suggested in https://github.com/libopencm3/libopencm3/pull/399
At least provide macros for each family that allows easy masking of the
full set of reset reason flags. Trying to provide a function that
provides these in random upper bits seems unclear at best.
Reserved bits are marked explicitly in the comments. ASCR defines
are changed to be consistent with the reference manual. HYSCR,
ASMR, CMR and CICR register defines are rewritten to be more
concise and readable.
For both v1 and v2, provide routines to help do arbitrary length
write/read transfers.
Tested with multiple byte writes and reads, for both 100khz and 400khz,
with repeated starts and stop/starts. However, only tested (presently)
with a single i2c target device, a Sensiron SHT21 sensor. Extended
testing against eeproms and alternative devices would be useful
If you're interested in slightly underclocking or midrange speeds,
you're into custom environments. Drop all the "helpers" for these odd
speeds. This is not the max speed for any existing f0 part.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
The following four new functions enable clocking SoC from HSE crystal:
rcc_clock_setup_in_hse_8mhz_out_{8,16,32,48}mhz
These functions start HSE as external clock and feed its output to PLL
if higher frequency is needed.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
-> Dropped 8,16,32Mhz functions as superfluous.
Early revisions of the reference manuals used different names for the
touch sense controller and firewall bits. These have now been changed
to be more in line with other families, and as these parts and bits were
new in this library, simply move forward to the current naming
convention.
According to reference manuals both l0 and l4 have "v2" i2c peripheral.
This patch adds i2c support to l0 and l4 using previously unified "v2" i2c
headers and implementation.
No real hardware has been tested so far. Only compilation tests for both
libopencm3 and libopencm3-examples for all stm32 families.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
The f1, f2, f4, l1 chip families have a similar "v1" i2c peripheral on board.
More recent f0, f3, l0, l3 chip families share another "v2" version of i2c.
This patch unifies headers and implementation for two types of i2c peripherals:
- rename: i2c_common_all.[ch] to i2c_common_v1.[ch]
- remove i2c_common_f24.h: extra I2C blocks are defined in specific headers
- use f3 i2c code as a basis for common "v2" i2c implementation
- add f0 i2c support: use "v2" i2c implementation
Tests:
- tested on a custom f0 board
- compile-tested both libopencm3 and libopencm3-examples for all stm32
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Add three more RTC clock helper functions:
- rcc_set_rtc_clock_source
RTC on stm32/f0 can be clocked from the following three
sources: LSI, LSE (32.768Hz), HSE/32.
- rcc_enable_rtc_clock
- rcc_disable_rtc_clock
enable/disable clocking RTC module using selected clock source
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Add clock config for the 25MHz crystal found on the discovery board.
Verified to work on the STM32F7-Disco.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Modified namespaces and types->structs to avoid namespace pollution as
was fixed for other families in:
3a7cbec7: stm32l/stm32f: name space standardization [BREAKING]
It was never complete, even for F1 family code, and went on to be even
less complete for f0 and f3. The usefulness of a library function to
check for both the irq being enabled _and_ the status flag is highly
questionable, and caused known user confusion.
The existing, much simpler, and fully functional usart_get_flag() is
a good replacement in almost all sane use cases.
Fixes https://github.com/libopencm3/libopencm3/issues/734
Simplified blocking API, with an async routine if you really need it.
Follows as best as I can understand the reference manual, but testing
those conditions will be difficult.
SHCSR and DFSR are only implement on ARMv6 if the "Debug extension" is
implemented, but that's pretty much everywhere, so allow access to the
defines.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Some parts used HSICLK, some used HSI. Most used NOCLK, f3 used
DISABLED. Try and move all to the shorter, simpler forms, instead of
having mixed defines for different targets for the same thing. Just
because the bits themselves are different doesn't mean we should make it
more difficult for users to port code.
MCOPRE prescaler definitions used a _SHIFT and a preshiftd definition.
The rest of the file uses separate _MASK and _SHIFT definitions.
Fix whitespace on the definitions while we're here.
The f107 ethernet peripheral is the same as in f4, and was pulled out
into lib/ethernet/mac_stm32fxx7.c in 52758bb8fd
This drops the duplicate code.
Fixes Github issue #694
The TSVREFE bit is defined to only be present on ADC1, so drop the
pointless adc argument. This has the added benefit of making the
API consistent with all other STM32 adc parts.
Use same names as adv-v2 peripheral uses. F1 is the only v1 peripheral
adc that has calibration modes at all.
Old:
adc_calibration(ADC1); // blocking call
New (blocking):
adc_calibrate(ADC1);
New (asynch):
adc_calibrate_async(ADC1);
// do stuff
adc_is_calibrating(ADC1); // false when calibration finished
Old routines are preserved but marked deprecated for now.
Extract the calibration code from the f0, and share it with the other
adc-v2 peripheral users (f0,l0,f3,l4)
Uses the same naming set of is/async naming conventions requested by the
RTOS guys instead of having blocking only calls.
Old code:
adc_calibrate_start(ADC);
adc_calibrate_wait_finish(ADC);
New code (blocking):
adc_calibrate(ADC);
New code (asynch):
adc_calibrate_async(ADC);
// do stuff
adc_is_calibrating(ADC); // will be false when it's finished.
Old code for f0 is still available, but marked deprecated.
Start providing async routines for all blocking routines, to make it
easier to use libopencm3 in some RTOS environments. This is not in
anyway intended to be complete, this just covers a single blocking
routine, rcc_wait_for_osc_ready. Documentation added to the top level,
and provided for all stm32 families.
Thoughts: should this be a "sam0" family rather than samd? (Much like Atmel's
own software package lumps all the cortex-m0+ devices in one family)
This was enough to get a basic blinky working at least.
Karl Palsson