We don't need groupings around each enum, they format nicely into a
section already. Likewise, the doxygen _is_ documentation, so we don't
need extra versions of it in places. Also fix a few warnings generated.
rtc_common_all never existed, and f3 has the same "v2" peripheral used
by ~all parts other than the f1. We don't have any f3 rtc test code,
but the existing code was clearly wrong, and this is at least including
the correct basic defines.
Fixes: https://github.com/libopencm3/libopencm3/issues/1106
Unlike with the doxygen source generation, we can't autoguess which of
the class files are eligible automatically. Instead, make a stub hid
file, (which we can now start adding to, if desired) and include it in
all builds that include other class stubs.
* Conforms mostly to the STM32 GPIO API where possible.
* Supports pin configuration (direction, pull-up/down, etc.) as well
as pinmux configuration.
* Supports set/clear/get operations to the GPIO port/pins.
* Created base doxy header and groups to align with existing formatting.
Updates to a base set of includes to map to the h7 include files which are
mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO).
Custom files that have been implemented from the datasheet/ref manual include
the memory map, RCC, PWR definitions, and irq.json file for generation of
nvic files for interrupt mapping.
Additional functionality, especially PLL and tweaks for non-F7 compatible
implementations coming in future commits.
Added documentation tree configuration.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Changed dmaX_streamX to dmaX_strX in a few places for consistency
v2 "single" peripheral with a couple of tweaks :
- added registers to configure two additionnal advanced analog watchdog.
- different adc sampling time time based on channel groups.
- 8 steps adc sequence injection, using chselr/chselrmode.
And a note on the rm explaining that after every configuration change to ADC_CFGR1's
SCANDIR or CHSELRMOD or CHSELR register, user need to check that configuration
is applied before any other modification / adc conversion start.. making adc_set_reqular
a bit painfull to read..
DMAMUX peripheral is a dma request router/trigger, present on g0, wb, h7 and l4+.
Basically it allows to easily map peripheral requests to whatever dma channel we
want to use (similarily to the DMA_CSELR register, but without limitation) but,
it also also adds some clever dma request synchronization and even some dma request
generation logic via internal request generator "channels", allowing some requests
chaining, or triggering reqs from non dma capable peripherals.
nb: g0 only features 1 dmamux bloc, supports 7 irq and 4 generators, l4+ supports 13
dma channels and 3 generators and h7 has two dmamuxes, with support for the 15 dma
channels and 7 generators - so as much CxCR and RGxCR register - but they are bit
to bit compatible - excluding of course the sync/sig and dma requests id mappings.
btw, currently, request generator channels are defined in common header, but maybe
we should define them in device header ? or we dont care (like for dma channels,
only defined in dma_f24 but not for other devices ?).
See ST AN5224 for more information
same same, bit for bit, except not ;) - Channel request mapping now
depends on a new DMAMUX peripheral, and there's no default preset.
So, before enabling dma channel after its configuration, request
must be configured by :
dmamux_set_dma_channel_request(DMAMUX1, DMA_CHANNELx, request_number_from_datasheet);
Updates the main memory map and the makefile.
Adds the SWM050 to devices.data, so that a linker script can be automatically generated.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
I apparently based memorymap.h on previously written header without noticing
that g0 has only one apb despite a big hole in the memory space and addresses
matching usual apb1/apb2 split..
Add basically what's needed to have some minimal but usefull subset of
function for a timer: irqs, compare, period, out polarity, enable/disable
and start.
Fix some direct includes, tag properly, include a stub file to pull in
shared header documentation and re-arrange some existing documentation
to make it present nicely.
Was completely undocumented before. Just needed different tagging so it
could be picked up.
No attempt at this stage of sharing more code between the cmu modules.
gpio_common was built, but wasn't picked up by any documentation.
Use the peripheral_apis style from stm32, but try out the #pragma once
style. Downside is you don't get warnings if you include an sub layer
.h file. Upsides are
* no ifdef/endif blocks
* no /**@cond*/ /**@endcond*/ blocks
* that's enough win!
F09x and L4 share the same cselr register, as well as some L0s, factorize
definitions in a new shared header and add helpers.
fyi, that register allows to redefine dma channel peripheral mapping - see
device datasheet for mapping tables.
Regular rng peripheral, with one additional bit : clock error detection
apparently available on l4 chips). Curiously, Clock error detection is
_disabled_ when bit is set, but bit is cleared by default, so peripheral
/ clock error detection behaves like all other chips..
NB: RNG need proper rcc_ccicr_rngsel bits set to work, no clock is set by
default. Note also that on that chip fRNGCLK must be higher than fHCLK/32
You can't have two mainpage items, and the second was just being
ignored. This restores them, which makes the left side list longer,
which we may or may not like, but it's at least how it was documented to
be.
The internal stack has a hard internal limit of 8, which is as many as
all supported devices support, but not as flexible as the arbitrary
addressing that USB actually allows.
At _least_ document this.
Fixes: https://github.com/libopencm3/libopencm3/issues/666
* Include the doc-swm050.h core file that defines the base groups.
* Fix/tweak groupings to make things consistent with other targets.
* Drop redundant type information. That's all included from the function
signatures automatically by doxygen.
* Added register descriptions from datasheet.
SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a
Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals
are GPIO, Timer and WDT. There's only two parts in this series, with
either TSSOP-8 or SSOP-16 packages.
This commit introduces the interrupt vector and GPIO support for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This clock is the USB High Frequency PLL that gets trimmed based
on clock recovery. It is the most accurate PLL on the system,
assuming it is connected via USB.
Add the definition of this clock in preparation for being able
to switch to it.
Signed-off-by: Sean Cross <sean@xobs.io>
According to RM0351 and RM0394 flash needs to be programmed by double words.
Also fix flash_program() which was wrong anyways.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
48Mhz has no purpose other than to be a naiive method of haivng working
USB. 120MHz never had any purpose, other than to match the f2 code it
was copied from. Drop them both. Remaining configs are all max speeds
for various F4 parts. Lower speeds are all custom
Some families had partially moved to peripheral api, and others were
only documenting common code, but not specific code. Delete dummy .c
files, and check that all specific apis are also being documented, not
just common apis.
Functions that are already documented in the top level common api.h file
won't add any more documentation from later .c files. Keep docs for
part specifics, in the .h files where they're accessible to IDEs and
also the documentation generation, and drop all (including the redundant
ones) from the .c file.
Karl Palsson