Commit Graph

20 Commits

Author SHA1 Message Date
Guillaume Revaillot f121c8c8f0 .gitignore: ignore autogenerated include/libopencmsis/swm050/ 2019-06-17 22:34:15 +00:00
Icenowy Zheng 54eff24e7c swm050: new MCU family
SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a
Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals
are GPIO, Timer and WDT. There's only two parts in this series, with
either TSSOP-8 or SSOP-16 packages.

This commit introduces the interrupt vector and GPIO support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2019-06-05 20:25:43 +00:00
Guillaume Revaillot b8d4b03722 stm32g0: add base, irqs, memorymap and current devices. 2019-05-20 23:43:41 +00:00
Karl Palsson 8a952d8476 gd32: drop commit of generated code 2019-05-19 21:39:46 +00:00
Icenowy Zheng 330d5fd5be gd32: add new chip series f1x0
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.

Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.

From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage.  We can
see where they move in the future.
2019-04-03 12:53:33 +00:00
Karl Palsson 6e65170390 cmsis: add new families to dispatch handlers.
Some people use the opencmsis headers.  Update them to include all the
recently added targets.

Fixes: https://github.com/libopencm3/libopencm3/pull/907
2018-04-13 11:15:32 +00:00
Karl Palsson d3e228176f libopencmsis: Fill in missing CMSIS interrupt links
And correct a minor typo in the generated code.
2014-05-14 16:11:43 +00:00
Forrest Voight 8dcf21e755 replaced placeholder __(en|dis)able_irq efm32_int functions with working ones 2013-11-07 21:58:22 +00:00
Piotr Esden-Tempski 7df63fcae0 First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
2013-06-12 18:22:56 -07:00
chrysn ab5a544d45 added irqs for the rest of the efm32 devices 2012-10-19 01:11:43 +02:00
chrysn d526dd3268 rename tinygecko->efm32tg everywhere 2012-10-19 00:59:49 +02:00
chrysn d13043d787 change discriminator in efm32 series from TINYGECKO to EFM32TG 2012-10-19 00:31:10 +02:00
chrysn a818dbe729 use generalized libopencm3 functions in cmsis 2012-10-19 00:18:49 +02:00
chrysn 99975d9a05 comment updates 2012-04-29 03:05:27 +02:00
chrysn 9324f00038 enhanced cmsis again for other efm32tg examples 2012-04-29 00:18:03 +02:00
chrysn 4a36d23d8c more irq/isr translations 2012-04-27 17:00:24 +02:00
chrysn dfbb7912c3 additions to opencmsis to make the clock example run 2012-04-27 15:55:43 +02:00
chrysn c9b074a120 sys tick cmsis interface for blink example 2012-04-27 15:21:59 +02:00
chrysn 286af7f26e new requirements form emlib and -examples 2012-04-27 14:10:29 +02:00
chrysn 8359caff3b moved core_cm3.h to more general location 2012-04-22 22:07:01 +02:00