Commit Graph

12 Commits

Author SHA1 Message Date
Matt Anderson d8579dde95 CortexM0: IPR and SHPR are only word addressable
For ARMv6M, the IPR and SHPR registers are accessible only when
adddressed with a 32bit word read or write.

Currently in libopencm3 all NVIC interrupt priority register accesses
are made using an 8bit read or write, which results in the hardware
ignoring the write or always returning 0 on read.

Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and
conditional implementation of nvic_set_priority when building for
cortex-m0.

See ARMv6M developer documentation:
IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html
SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html
2019-10-17 21:26:13 +00:00
Karl Palsson 60991ac306 doc: cm3: nvic: convert existing docs to doxygen
Make it visible
2019-06-25 21:15:19 +00:00
Karl Palsson 69ce9f876f doc: core cm3: standard titles
easier on the eyes reading the list of docs
2019-06-25 21:15:19 +00:00
Jim Paris 01f08c4638 Remove WEAK from handler prototypes
These prototypes affect functions defined by application code.  Only
the implementations in libopencm3 are supposed to be weak; the
functions in application code should definitely not be.  Otherwise,
you'll end up with two weak symbols being linked together, and
it's luck as to which one the linker picks.
2015-11-24 09:55:27 +00:00
Karl Palsson c72f3d588a Surround all macro parameters with ()
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
2015-10-14 22:15:15 +00:00
BuFran e1ebcc9da8 [Cortex] Add preliminary support for core-dependent defines ARMv6m / ARMv7m, ARMv7em 2013-08-22 17:18:35 -07:00
Piotr Esden-Tempski 34de1e776e Changed to use stdint types. 2013-06-12 19:11:22 -07:00
Piotr Esden-Tempski 7df63fcae0 First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
2013-06-12 18:22:56 -07:00
Piotr Esden-Tempski 3d3ddc7014 Fixed all warnings for examples. 2013-02-26 19:33:42 -08:00
Ken Sarkies 35c0863a75 Documentation updates 2012-11-12 21:44:52 +10:30
chrysn f705d1cd6e dispatch for chip specific nvic 2012-10-18 12:46:30 +02:00
chrysn 837de3ff97 nvic.h factored out (incomplete) 2012-10-18 10:27:51 +02:00