Commit Graph

9 Commits

Author SHA1 Message Date
Karl Palsson 3ebd71b464 cm3: extract Coresight LSR/LAR definitions
Use a single point of definition for the offset, and add it where it was
missing.
2019-10-18 22:29:13 +00:00
Karl Palsson f4d6da9554 cm3: MPU is optional on both v6m and v7m.
The MPU is an implementation option available for both ARMv6-M and ARMv7-M.
Remove poorly merged code that attempted to include this only for cortex m0+.

Added doxygen, updated the definitions of the RBAR register, (though if you're
really using this periperhal, you should be looking at the ref man for further
information)

Reported-by: forrestv on irc.
2015-08-16 13:35:35 +00:00
Stefan Agner 7681597e42 Use type suffix to avoid warnings
When compiling with all warnings enabled, some defines can lead to
warning due to missing unsigned type suffix:

warning: integer overflow in expression [-Woverflow]

This fix should not affected behavior at all, since calculation with
such overflows lead to the same actual address when writing to that
location. However, it makes the warning disappear and also defines
the right data type for a memory location.
2014-02-06 00:59:39 +01:00
Karl Palsson ec9fc5c122 [swo] Add/Update definitions necessary for SWO to work
ITM Stimulus ports need to be accessible with different sizes

The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO

Note: this is an API change for doing 32bit writes.
Old:
    ITM_STIM[stimulus_port] = value
New:
    ITM_STIM32(stimulus_port) = value

This api is much more in common with some of the other registers that
behave this way.  As there's very little (if any) code already using
this API, it's a good time to fix it permanently.

Remove misleading ITM register definitions

ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well.  There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.

Lock and lock status register definitions were added, as per ARM:
  "For ARMv7-M, the component ID registers are required for the ROM table,
   and the CoreSight management lock access mechanism is defined for the
   DWT, ITM, FPB and TPIU blocks."
2013-11-21 16:21:38 +00:00
BuFran e1ebcc9da8 [Cortex] Add preliminary support for core-dependent defines ARMv6m / ARMv7m, ARMv7em 2013-08-22 17:18:35 -07:00
Piotr Esden-Tempski 43561de329 License change of the library to LGPL, version 3 or later.
Agreed to by all the significant contributors to the library.
2012-03-02 14:44:49 -08:00
Gareth McMullin f0a1282d42 Added ITM and TPIU register definitions. 2011-02-17 21:38:38 +13:00
Uwe Hermann 559bc52fa4 Add some missing LIBOPENCM3_ prefixes. 2011-02-09 01:36:06 +01:00
Uwe Hermann 8f251e8a9d Some more file/path restructuring.
All #includes now explicitly use the "<libopencm3/stm32/rcc.h>" format.
If you want to get rid of the "libopencm3" prefix in your local project you
can add a respective -I entry in your Makefile (not recommended though).

All .ld files and .a libs are installed in $(TOOLCHAIN_DIR)/lib
directly (as before), but are now renamed to avoid potential
conflicts now or in the future. Examples:

  libopencm3_lpc13xx.a
  libopencm3_lpc13xx.ld
  libopencm3_stm32.a
  libopencm3_stm32.ld
2010-12-31 18:18:39 +01:00