sam3x: Add some PMC convenience functions.
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@ -68,6 +68,11 @@
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#define EEFC_FSR_FCMDE (0x01 << 1)
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#define EEFC_FSR_FRDY (0x01 << 0)
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static inline void eefc_set_latency(u8 wait)
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{
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EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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}
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#endif
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@ -125,6 +125,15 @@
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#define PMC_SR_LOCKA (0x01 << 1)
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#define PMC_SR_MOSCXTS (0x01 << 0)
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enum mck_src {
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MCK_SRC_SLOW = 0,
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MCK_SRC_MAIN = 1,
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MCK_SRC_PLLA = 2,
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MCK_SRC_UPLL = 3,
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};
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void pmc_mck_set_source(enum mck_src src);
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void pmc_xtal_enable(bool en, u8 startup_time);
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void pmc_plla_config(u8 mul, u8 div);
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void pmc_peripheral_clock_enable(u8 pid);
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void pmc_peripheral_clock_disable(u8 pid);
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@ -19,9 +19,20 @@
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#include <libopencm3/sam3x/pmc.h>
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void pmc_xtal_enable(bool en, u8 startup_time)
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{
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if (en) {
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CKGR_MOR |= CKGR_MOR_KEY |
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CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST_MASK;
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while (!(PMC_SR & PMC_SR_MOSCXTS));
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} else {
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CKGR_MOR = CKGR_MOR_KEY | (CKGR_MOR & ~CKGR_MOR_MOSCXTEN);
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}
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}
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void pmc_plla_config(u8 mul, u8 div)
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{
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CKGR_PLLAR = CKGR_PLLAR_ONE | (mul << 16) |
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CKGR_PLLAR = CKGR_PLLAR_ONE | ((mul - 1) << 16) |
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CKGR_PLLAR_PLLACOUNT_MASK | div;
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while (!(PMC_SR & PMC_SR_LOCKA));
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}
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@ -42,3 +53,9 @@ void pmc_peripheral_clock_disable(u8 pid)
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PMC_PCDR1 = 1 << (pid & 31);
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}
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void pmc_mck_set_source(enum mck_src src)
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{
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PMC_MCKR = (PMC_MCKR & ~PMC_MCKR_CSS_MASK) | src;
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while (!(PMC_SR & PMC_SR_MCKRDY));
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}
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