Spellchecking fixes.
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169dbd6c08
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fb5c86db07
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@ -41,7 +41,7 @@ LGPL License Terms @ref lgpl_license
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/* --- Convenience macros -------------------------------------------------- */
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/* CAN register base adresses (for convenience) */
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/* CAN register base addresses (for convenience) */
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/*****************************************************************************/
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/** @defgroup can_reg_base CAN register base address
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@ingroup can_defines
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@ -77,9 +77,9 @@ BEGIN_DECLS
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void crc_reset(void);
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/**
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* Add a word to the crc calculator and return the result.
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* @param data new word to add to the crc calculator
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* @return final crc calculator value
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* Add a word to the CRC calculator and return the result.
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* @param data new word to add to the CRC calculator
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* @return final CRC calculator value
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*/
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uint32_t crc_calculate(uint32_t data);
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@ -248,7 +248,7 @@ specific memorymap.h header before including this header file.*/
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/* --- GPIOx_AFRL/H values ------------------------------------------------- */
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/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
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/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
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/* See datasheet table 6 (pg. 48) for alternate function mappings. */
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#define GPIO_AFR(n, af) (af << ((n) * 4))
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#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
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@ -39,7 +39,7 @@ specific memorymap.h header before including this header file.*/
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/* --- Convenience macros -------------------------------------------------- */
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/* I2C register base adresses (for convenience) */
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/* I2C register base addresses (for convenience) */
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/****************************************************************************/
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/** @defgroup i2c_reg_base I2C register base address
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@ingroup i2c_defines
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@ -109,7 +109,7 @@ specific memorymap.h header before including this header file.*/
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/* PEC: Packet error checking */
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#define I2C_CR1_PEC (1 << 12)
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/* POS: Acknowledge / PEC postition */
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/* POS: Acknowledge / PEC position */
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#define I2C_CR1_POS (1 << 11)
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/* ACK: Acknowledge enable */
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@ -342,7 +342,7 @@ specific memorymap.h header before including this header file.*/
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* TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
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*/
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/* --- I2C const definitions ----------------------------------------------- */
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/* --- I2C constant definitions -------------------------------------------- */
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/****************************************************************************/
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/** @defgroup i2c_rw I2C Read/Write bit
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@ -353,7 +353,7 @@ specific memorymap.h header before including this header file.*/
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#define I2C_READ 1
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/**@}*/
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/* --- I2C funtion prototypes----------------------------------------------- */
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/* --- I2C function prototypes---------------------------------------------- */
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BEGIN_DECLS
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@ -70,7 +70,7 @@ specific memorymap.h header before including this header file.*/
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/* PR[2:0]: Prescaler divider */
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#define IWDG_PR_LSB 0
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/** @defgroup iwdg_prediv IWDG Prescaler divider
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/** @defgroup iwdg_prediv IWDG prescaler divider
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@ingroup STM32F_iwdg_defines
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@{*/
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@ -45,7 +45,7 @@ specific memorymap.h header before including this header file.*/
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/* RNG ENABLE */
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#define RNG_CR_RNGEN (1 << 2)
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/* RNG interupt enable */
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/* RNG interrupt enable */
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#define RNG_CR_IE (1 << 3)
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/* --- RNG_SR values ------------------------------------------------------- */
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@ -59,10 +59,10 @@ specific memorymap.h header before including this header file.*/
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/* Seed error current status */
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#define RNG_SR_SECS (1 << 2)
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/* Clock error interup status */
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/* Clock error interrupt status */
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#define RNG_SR_CEIS (1 << 5)
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/* Seed error interup status */
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/* Seed error interrupt status */
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#define RNG_SR_SEIS (1 << 6)
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#endif
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@ -40,7 +40,7 @@ specific memorymap.h header before including this header file.*/
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/* --- Convenience macros -------------------------------------------------- */
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/* Timer register base adresses (for convenience) */
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/* Timer register base addresses (for convenience) */
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/****************************************************************************/
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/** @defgroup tim_reg_base Timer register base addresses
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@ingroup timer_defines
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@ -235,7 +235,7 @@ specific memorymap.h header before including this header file.*/
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/* LBDL: LIN break detection length */
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#define USART_CR2_LBDL (1 << 5)
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/* ADD[3:0]: Addres of the usart node */
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/* ADD[3:0]: Address of the usart node */
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#define USART_CR2_ADD_MASK 0xF
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/* --- USART_CR3 values ---------------------------------------------------- */
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@ -39,7 +39,7 @@
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BEGIN_DECLS
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/**
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* Read the onboard flash size
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* Read the on board flash size
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* @return flash size in KB
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*/
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uint16_t desig_get_flash_size(void);
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@ -448,7 +448,7 @@ and ADC2
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#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
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/** Timer 5 Trigger Output */
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#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
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/** Timer53 Compare Output 4 */
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/** Timer 5 Compare Output 4 */
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#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
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/** Injected Software Trigger */
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#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
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@ -457,7 +457,7 @@ and ADC2
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#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
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#define ADC_CR2_JEXTSEL_SHIFT 12
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/* ALIGN: Data alignement. */
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/* ALIGN: Data alignment. */
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#define ADC_CR2_ALIGN_RIGHT (0 << 11)
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#define ADC_CR2_ALIGN_LEFT (1 << 11)
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#define ADC_CR2_ALIGN (1 << 11)
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@ -603,9 +603,9 @@ and ADC2
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#define ADC_JSQR_JSQ2_LSB 5
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#define ADC_JSQR_JSQ1_LSB 0
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/* JL[2:0]: Discontinous mode channel count injected channels. */
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/* JL[2:0]: Discontinuous mode channel count injected channels. */
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/****************************************************************************/
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/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro
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/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode from
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injected channels.
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@ingroup adc_defines
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@ -137,14 +137,14 @@
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#define ETH_MACFCR_ZQPD 0x00000080
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#define ETH_MACFCR_PT 0xFFFF0000
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/* Ethernet MAC interrupt status regster ETH_MACSR bits */
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/* Ethernet MAC interrupt status register ETH_MACSR bits */
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#define ETH_MACSR_PMTS 0x0008
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#define ETH_MACSR_MMCS 0x0010
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#define ETH_MACSR_MMCRS 0x0020
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#define ETH_MACSR_MMCTS 0x0040
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#define ETH_MACSR_TSTS 0x0200
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/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */
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/* Ethernet MAC interrupt mask register ETH_MACIMR bits */
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#define ETH_MACIMR_PMTIM 0x0008
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#define ETH_MACIMR_TSTIM 0x0200
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@ -780,33 +780,33 @@ Line Devices only
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/* ADC2_ETRGREG_REMAP: */
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/**
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* ADC2 external trigger regulator conversion remapping
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* (only low-, medium-, high- and XL-densitiy devices)
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* (only low-, medium-, high- and XL-density devices)
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*/
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#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
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/* ADC2_ETRGINJ_REMAP: */
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/**
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* ADC2 external trigger injected conversion remapping
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* (only low-, medium-, high- and XL-densitiy devices)
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* (only low-, medium-, high- and XL-density devices)
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*/
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#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
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/* ADC1_ETRGREG_REMAP: */
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/**
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* ADC1 external trigger regulator conversion remapping
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* (only low-, medium-, high- and XL-densitiy devices)
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* (only low-, medium-, high- and XL-density devices)
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*/
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#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
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/* ADC1_ETRGINJ_REMAP: */
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/**
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* ADC1 external trigger injected conversion remapping
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* (only low-, medium-, high- and XL-densitiy devices)
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* (only low-, medium-, high- and XL-density devices)
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*/
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#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
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/* TIM5CH4_IREMAP: */
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/** TIM5 channel4 internal remap */
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/** TIM5 channel 4 internal remap */
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#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
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/* PD01_REMAP: */
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@ -24,7 +24,7 @@
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/* --- STM32 specific peripheral definitions ------------------------------- */
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/* Memory map for all busses */
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/* Memory map for all buses */
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#define FLASH_BASE ((uint32_t)0x08000000)
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#define PERIPH_BASE ((uint32_t)0x40000000)
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#define INFO_BASE ((uint32_t)0x1ffff000)
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@ -155,7 +155,7 @@ LGPL License Terms @ref lgpl_license
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/* ADCPRE: ADC prescaler */
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/****************************************************************************/
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/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
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/** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values
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@ingroup STM32F1xx_rcc_defines
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@{*/
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@ -166,7 +166,7 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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/* PPRE2: APB high-speed prescaler (APB2) */
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/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
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/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors
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@ingroup STM32F1xx_rcc_defines
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@{*/
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@ -178,7 +178,7 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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/* PPRE1: APB low-speed prescaler (APB1) */
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/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
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/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors
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@ingroup STM32F1xx_rcc_defines
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@{*/
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@ -190,7 +190,7 @@ LGPL License Terms @ref lgpl_license
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/**@}*/
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/* HPRE: AHB prescaler */
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/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
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/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors
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@ingroup STM32F1xx_rcc_defines
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@{*/
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@ -32,7 +32,7 @@ LGPL License Terms @ref lgpl_license
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*/
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/*
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* The F1 RTC is a straight timestamp, a completely different peripheral to
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* The F1 RTC is a straight time stamp, a completely different peripheral to
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* that found in the F2, F3, F4, L1 and F0.
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*/
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@ -43,7 +43,7 @@ LGPL License Terms @ref lgpl_license
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/* --- USB base addresses -------------------------------------------------- */
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/* USB packet buffer memory base addr. */
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/* USB packet buffer memory base address. */
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#define USB_PMA_BASE 0x40006000L
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/* --- USB general registers ----------------------------------------------- */
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@ -104,12 +104,12 @@ LGPL License Terms @ref lgpl_license
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#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
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#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
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/* --- USB device addres register masks / bits ----------------------------- */
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/* --- USB device address register masks / bits ---------------------------- */
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#define USB_DADDR_ENABLE 0x0080
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#define USB_DADDR_ADDR 0x007F
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/* --- USB device addres register manipulators ----------------------------- */
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/* --- USB device address register manipulators ---------------------------- */
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/* --- USB endpoint register offsets --------------------------------------- */
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@ -123,7 +123,7 @@
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/* FACCEN: Flash access enable */
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#define FSMC_BCR_FACCEN (1 << 6)
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/* MWID[5:4]: Memory databus width */
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/* MWID[5:4]: Memory data bus width */
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#define FSMC_BCR_MWID (1 << 4)
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/* MTYP[3:2]: Memory type */
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@ -330,7 +330,7 @@
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#define OTG_FS_DOEPINTX_EPDISD (1 << 1)
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#define OTG_FS_DOEPINTX_XFRC (1 << 0)
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/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */
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/* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0) */
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/* Bit 31 - Reserved */
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#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
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#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
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@ -384,7 +384,7 @@
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#define OTG_HS_DOEPINTX_EPDISD (1 << 1)
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#define OTG_HS_DOEPINTX_XFRC (1 << 0)
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/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */
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/* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_HS_DOEPTSIZ0) */
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/* Bit 31 - Reserved */
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#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
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#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
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@ -182,7 +182,7 @@
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/* DBLOCKSIZE: Data block size */
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/* SDIO_DCTRL_DBLOCKSIZE_n
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* blocksize is 2**n bytes with 0<=n<=14
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* block size is 2**n bytes with 0<=n<=14
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*/
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#define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4
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#define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
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/* DMAEN: DMA enable bit */
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#define SDIO_DCTRL_DMAEN (1 << 3)
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/* DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte transfer */
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/* DTMODE: Data transfer mode selection 1: Stream or SDIO multi byte transfer */
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#define SDIO_DCTRL_DTMODE (1 << 2)
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/* DTDIR: Data transfer direction selection */
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*
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* This means that we look at the bits in the bit window designated by
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* the mask. If the bit in the masked window is not matching the
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* bitmask BIT then we write 1 and if the bit in the masked window is
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* matching the bitmask BIT we write 0.
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* bit mask BIT then we write 1 and if the bit in the masked window is
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* matching the bit mask BIT we write 0.
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*
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* TODO: We may need a faster implementation of that one?
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*/
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/* EWIF: Early wakeup interrupt flag */
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#define WWDG_SR_EWIF (1 << 0)
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/* --- WWDG funtion prototypes---------------------------------------------- */
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/* --- WWDG function prototypes---------------------------------------------- */
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/* TODO */
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