doc: msp432/e4: Fix groupings for doxygen
Proper closing tags, an outer grouping, and don't refer to missing groups.
This commit is contained in:
Karl Palsson
parent
056602b12a
commit
fa7a908027
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@ -34,12 +34,13 @@
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#ifndef MSP432E4_SYSTEMCONTROL_H
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#define MSP432E4_SYSTEMCONTROL_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/msp432/e4/memorymap.h>
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#include <stdbool.h>
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/** @defgroup sysctl_registers SYSCTL Registers
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* @ingroup sysctl_defines
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* @brief System Control Registers
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@{*/
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/** Device Identification 0 */
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@ -436,10 +437,9 @@
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#define SYSCTL_UNIQUEID2 MMIO32(SYSCTL_BASE + 0xF28)
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/** Unique ID 3 */
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#define SYSCTL_UNIQUEID3 MMIO32(SYSCTL_BASE + 0xF2C)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_did0_values SYSCTL_DID0 Values
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* @ingroup sysctl_registers
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* @brief System Control Device Identification 0 Register Values
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@{*/
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/** DID0 Version Shift */
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@ -458,10 +458,9 @@
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#define SYSCTL_DID0_MINOR_SHIFT (0)
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/** Minor Revision Mask */
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#define SYSCTL_DID0_MINOR_MASK (0xFF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_did1_values SYSCTL_DID1 Values
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* @ingroup sysctl_registers
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* @brief System Control Device Identification 1 Register Values
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@{*/
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/** DID1 Version Shift */
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@ -514,10 +513,9 @@
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#define SYSCTL_DID1_QUAL_PILOT (0x1)
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/** Fully Qualified */
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#define SYSCTL_DID1_QUAL_QUALIFIED (0x2)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_ptboctl_values SYSCTL_PTBOCTL0 Values
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* @ingroup sysctl_registers
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* @brief System Control Power-Temp Brownout Control Register Values
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@{*/
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/** VDDA Under BOR Event Action Shift */
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@ -544,10 +542,9 @@
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#define SYSCTL_PTBOCTL_VDD_UBOR_NMI (0x2)
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/** VDD Under BOR Event Action - Reset */
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#define SYSCTL_PTBOCTL_VDD_UBOR_RESET (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_ric_values SYSCTL_RIS Values
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* @ingroup sysctl_registers
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* @brief System Control Raw Interrupt Status Register Values
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@{*/
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/** MOSC Power Up Raw Interrupt Status */
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@ -558,10 +555,9 @@
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#define SYSCTL_RIS_MOFRIS (1 << 3)
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/** Brown-Out Reset Raw Interrupt Status */
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#define SYSCTL_RIS_BORRIS (1 << 1)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_imc_values SYSCTL_IMC Values
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* @ingroup sysctl_registers
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* @brief System Control Interrupt Mask Control Register Values
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@{*/
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/** MOSC Power Up Raw Interrupt Mask */
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@ -572,10 +568,9 @@
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#define SYSCTL_IMC_MOFIM (1 << 3)
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/** Brown-Out Reset Raw Interrupt Mask */
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#define SYSCTL_IMC_BORIM (1 << 1)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_misc_values SYSCTL_MISC Values
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* @ingroup sysctl_registers
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* @brief System Control Masked Interrupt Status and Clear Register Values
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@{*/
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/** MOSC Power Up Raw Interrupt Status*/
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@ -586,10 +581,9 @@
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#define SYSCTL_MISC_MOFMIS (1 << 3)
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/** Brown-Out Reset Raw Interrupt Status */
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#define SYSCTL_MISC_BORMIS (1 << 1)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_resc_values SYSCTL_RESC Values
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* @ingroup sysctl_registers
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* @brief System Control Reset Cause Register Values
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@{*/
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/** MOSC Failure Reset */
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@ -608,20 +602,18 @@
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#define SYSCTL_RESC_POR (1 << 1)
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/** External Reset */
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#define SYSCTL_RESC_EXT (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_pwrtc_values SYSCTL_PWRTC Values
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* @ingroup sysctl_registers
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* @brief System Control Power-Temperature Cause Register Values
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@{*/
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/** VDDA Under BOR Status */
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#define SYSCTL_PWRTC_VDDA_UBOR (1 << 4)
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/** VDD Under BOR Status */
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#define SYSCTL_PWRTC_VDD_UBOR (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_nmic_values SYSCTL_NMIC Values
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* @ingroup sysctl_registers
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* @brief System Control NMI Cause Register Values
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@{*/
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/** MOSC Failure NMI */
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@ -636,10 +628,9 @@
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#define SYSCTL_NMIC_POWER (1 << 2)
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/** External Pin NMI */
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#define SYSCTL_NMIC_EXTERNAL (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_moscctl_values SYSCTL_MOSCCTL Values
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* @ingroup sysctl_registers
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* @brief System Control Main Oscillator Control Register Values
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@{*/
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/** Oscillator Range */
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@ -652,10 +643,9 @@
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#define SYSCTL_MOSCCTL_MOSCIM (1 << 1)
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/** Clock Validation for MOSC */
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#define SYSCTL_MOSCCTL_CVAL (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_rsclkcfg_values SYSCTL_RSCLKCFG Values
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* @ingroup sysctl_registers
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* @brief System Control Run and Sleep Mode Configuration Register Values
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@{*/
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/** Memory Timing Register Update */
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@ -690,10 +680,9 @@
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#define SYSCTL_RSCLKCFG_PSYSDIV_SHIFT (0)
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/** PLL System Clock Divisor Mask */
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#define SYSCTL_RSCLKCFG_PSYSDIV_MASK (0x3FF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_memtim0_values SYSCTL_MEMTIM0 Values
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* @ingroup sysctl_registers
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* @brief System Control Memory Timing Parameter Register 0 for Main Flash
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* and EEPROM Register Values
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*
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@ -791,10 +780,9 @@
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#define SYSCTL_MEMTIM0_FWS_6 (0x6)
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/** FWS - 7 wait state */
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#define SYSCTL_MEMTIM0_FWS_7 (0x7)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_altclkcfg_values SYSCTL_ALTCLKCFG Values
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* @ingroup sysctl_registers
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* @brief System Control Alternate Clock Configuration Register Values
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@{*/
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/** Alternate Clock Source Shift */
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@ -805,10 +793,9 @@
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#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC (0x3)
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/** Alternate Clock Source - LFIOSC */
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#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC (0x4)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_dsclkcfg_values SYSCTL_DSCLKCFG Values
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* @ingroup sysctl_registers
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* @brief System Control Deep Sleep Clock Configuration Register Values
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@{*/
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/** PIOSC Power Down */
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@ -829,10 +816,9 @@
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#define SYSCTL_DSCLKCFG_DSSYSDIV_SHIFT (0)
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/** Deep Sleep Clock Divisor Mask */
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#define SYSCTL_DSCLKCFG_DSSYSDIV_MASK (0x3FF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_divsclk_values SYSCTL_DIVSCLK Values
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* @ingroup sysctl_registers
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* @brief System Control Divisor and Source Clock Configuration Register Values
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@{*/
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/** DIVSCLK Enable */
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@ -853,10 +839,9 @@
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#define SYSCTL_DIVSCLK_DIV_1 (0x0)
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/** Divisor Value - 2 */
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#define SYSCTL_DIVSCLK_DIV_2 (0x1)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_sysprop_values SYSCTL_SYSPROP Values
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* @ingroup sysctl_registers
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* @brief System Control System Properties Register Values
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@{*/
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/** LDO Sleep Mode Enable */
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@ -875,10 +860,9 @@
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#define SYSCTL_SYSPROP_LDOSEQ (1 << 5)
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/** FPU Present */
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#define SYSCTL_SYSPROP_FPU (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_piosccal_values SYSCTL_PIOSCCAL Values
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* @ingroup sysctl_registers
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* @brief System Control Precision Internal Oscillator
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* Calibration Register Values
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@{*/
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@ -892,10 +876,9 @@
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#define SYSCTL_PIOSCCAL_UT_SHIFT (0)
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/** User Trim Value Mask */
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#define SYSCTL_PIOSCCAL_UT_MASK (0x7F)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_pioscstat_values SYSCTL_PIOSCSTAT Values
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* @ingroup sysctl_registers
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* @brief System Control Precision Internal Oscillator
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* Statistics Register Values
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@{*/
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@ -917,10 +900,9 @@
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#define SYSCTL_PIOSCSTAT_CT_SHIFT (0)
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/** Calibration Value Mask */
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#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_pllfreq0_values SYSCTL_PLLFREQ0 Values
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* @ingroup sysctl_registers
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* @brief System Control PLL Frequency 0 Register Values
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@{*/
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/** PLL Power */
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@ -933,10 +915,9 @@
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#define SYSCTL_PLLFREQ0_MINT_SHIFT (0)
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/** PLL M Integer Value Mask */
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#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_pllfreq1_values SYSCTL_PLLFREQ1 Values
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* @ingroup sysctl_registers
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* @brief System Control PLL Frequency 1 Register Values
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@{*/
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/** PLL Q Value Shift */
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@ -947,18 +928,16 @@
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#define SYSCTL_PLLFREQ1_N_SHIFT (0)
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/** PLL N Value Mask */
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#define SYSCTL_PLLFREQ1_N_MASK (0x1F)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_pllstat_values SYSCTL_PLLSTAT Values
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* @ingroup sysctl_registers
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* @brief System Control PLL Status Register Values
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@{*/
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/** PLL Lock */
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#define SYSCTL_PLLSTAT_LOCK (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_slppwrcfg_values SYSCTL_SLPPWRCFG Values
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* @ingroup sysctl_registers
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* @brief System Control Sleep Power Configuration Register Values
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@{*/
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/** Flash Power Modes Shift */
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@ -979,10 +958,9 @@
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#define SYSCTL_SLPPWRCFG_SRAMPM_STANDBY (0x1)
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/** SRAM Power Mode - Low-Power Mode */
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#define SYSCTL_SLPPWRCFG_SRAMPM_LP (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_dslppwrcfg_values SYSCTL_DSLPPWRCFG Values
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* @ingroup sysctl_registers
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* @brief System Control Deep-Sleep Power Configuration Register Values
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@{*/
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/** LDO Sleep Mode */
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@ -1007,18 +985,16 @@
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#define SYSCTL_DSLPPWRCFG_SRAMPM_STANDBY (0x1)
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/** SRAM Power Mode - Low-Power Mode */
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#define SYSCTL_DSLPPWRCFG_SRAMPM_LP (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_nvmstat_values SYSCTL_NVMSTAT Values
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* @ingroup sysctl_registers
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* @brief System Control Non-Volatile Memory Information Register Values
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@{*/
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/** 32 Word Flash Write Buffer Available */
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#define SYSCTL_NVMSTAT_FWB (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_ldospctl_values SYSCTL_LDOSPCTL Values
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* @ingroup sysctl_registers
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* @brief System Control LDO Sleep Power Control Register Values
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@{*/
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/** Voltage Adjust Enable */
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@ -1041,10 +1017,9 @@
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#define SYSCTL_LDOSPCTL_VLDO_1_POINT_15 (0x17)
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/** LDO Out Voltage - 1.20V */
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#define SYSCTL_LDOSPCTL_VLDO_1_POINT_20 (0x18)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_ldospcal_values SYSCTL_LDOSPCAL Values
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* @ingroup sysctl_registers
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* @brief System Control LDO Sleep Power Calibration Register Values
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@{*/
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/** Sleep With PLL Shift */
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@ -1055,10 +1030,9 @@
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#define SYSCTL_LDOSPCAL_NOPLL_SHIFT (0)
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/** Sleep Without PLL Mask */
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#define SYSCTL_LDOSPCAL_NOPLL_MASK (0xFF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_ldodpctl_values SYSCTL_LDODPCTL Values
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* @ingroup sysctl_registers
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* @brief System Control LDO Deep-Sleep Power Control Register Values
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@{*/
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/** Voltage Adjust Enable */
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@ -1081,10 +1055,9 @@
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#define SYSCTL_LDODPCTL_VLDO_1_POINT_15 (0x17)
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/** LDO Out Voltage - 1.20V */
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#define SYSCTL_LDODPCTL_VLDO_1_POINT_20 (0x18)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_ldodpcal_values SYSCTL_LDODPCAL Values
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* @ingroup sysctl_registers
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* @brief System Control LDO Deep-Sleep Power Calibration Register Values
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@{*/
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/** Deep-Sleep Without PLL Shift */
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@ -1095,10 +1068,9 @@
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#define SYSCTL_LDODPCAL_30KHZ_SHIFT (0)
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/** Deep-Sleep With IOSC Mask */
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#define SYSCTL_LDODPCAL_30KHZ_MASK (0xFF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_sdpmst_values SYSCTL_SDPMST Values
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* @ingroup sysctl_registers
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* @brief System Control Sleep/Deep-Sleep Power Mode Status Register Values
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@{*/
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/** LDO Update Active */
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@ -1123,10 +1095,9 @@
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#define SYSCTL_SDPMST_FPDERR (1 << 1)
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/** SRAM Power Down Request Error */
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#define SYSCTL_SDPMST_SPDERR (1 << 0)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_resbehavctl_values SYSCTL_RESBEHAVCTL Values
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* @ingroup sysctl_registers
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* @brief System Control Reset Behavior Control Register Values
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@{*/
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/** Reset Operation - System Reset */
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@ -1149,10 +1120,9 @@
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#define SYSCTL_RESBEHAVCTL_EXTRES_SHIFT (2)
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/** EXT Reset Operation Mask */
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#define SYSCTL_RESBEHAVCTL_EXTRES_MASK (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_hssr_values SYSCTL_HSSR Values
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* @ingroup sysctl_registers
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* @brief System Control Hardware System Service Request Register Values
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@{*/
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/** Write Key Shift */
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@ -1169,10 +1139,9 @@
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#define SYSCTL_HSSR_CDOFF_NO_REQUEST (0x000000)
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/** Command Descriptor - Error Or Incomplete Request */
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#define SYSCTL_HSSR_CDOFF_ERROR (0xFFFFFF)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_usbpds_values SYSCTL_USBPDS Values
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* @ingroup sysctl_registers
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* @brief System Control USB Power Domain Status Register Values
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@{*/
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/** Memory Array Power Status Shift */
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@ -1193,10 +1162,9 @@
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#define SYSCTL_USBPDS_PWRSTAT_OFF (0x0)
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/** Power Domain Status - On */
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#define SYSCTL_USBPDS_PWRSTAT_ON (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_usbmpc_values SYSCTL_USBMPC Values
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* @ingroup sysctl_registers
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* @brief System Control USB Memory Power Control Register Values
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@{*/
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/** Memory Array Power Control Shift */
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@ -1209,10 +1177,9 @@
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#define SYSCTL_USBMPC_PWRCTL_SRAM_RET (0x1)
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/** Memory Array Power Control - On */
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#define SYSCTL_USBMPC_PWRCTL_ARR_ON (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_emacpds_values SYSCTL_EMACPDS Values
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* @ingroup sysctl_registers
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* @brief System Control Ethernet MAC Power Domain Status Register Values
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@{*/
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/** Memory Array Power Status Shift */
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@ -1231,10 +1198,9 @@
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#define SYSCTL_EMACPDS_PWRSTAT_OFF (0x0)
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/** Power Domain Status - On */
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#define SYSCTL_EMACPDS_PWRSTAT_ON (0x3)
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/*@}*/
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/**@}*/
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/** @defgroup sysctl_emacmpc_values SYSCTL_EMACMPC Values
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* @ingroup sysctl_registers
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* @brief System Control Ethernet MAC Memory Power Control Register Values
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@{*/
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/** Memory Array Power Control Shift */
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@ -1245,10 +1211,9 @@
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#define SYSCTL_EMACMPC_PWRCTL_ARR_OFF (0x0)
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/** Memory Array Power Control - On */
|
||||
#define SYSCTL_EMACMPC_PWRCTL_ARR_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup sysctl_lcdpds_values SYSCTL_LCDPDS Values
|
||||
* @ingroup sysctl_registers
|
||||
* @brief System Control LCD Power Domain Status Register Values
|
||||
@{*/
|
||||
/** Memory Array Power Status Shift */
|
||||
|
|
@ -1267,10 +1232,9 @@
|
|||
#define SYSCTL_LCDPDS_PWRSTAT_OFF (0x0)
|
||||
/** Power Domain Status - On */
|
||||
#define SYSCTL_LCDPDS_PWRSTAT_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup sysctl_lcdmpc_values SYSCTL_LCDMPC Values
|
||||
* @ingroup sysctl_registers
|
||||
* @brief System Control LCD Memory Power Control Register Values
|
||||
@{*/
|
||||
/** Memory Array Power Control Shift */
|
||||
|
|
@ -1281,10 +1245,9 @@
|
|||
#define SYSCTL_LCDMPC_PWRCTL_ARR_OFF (0x0)
|
||||
/** Memory Array Power Control - On */
|
||||
#define SYSCTL_LCDMPC_PWRCTL_ARR_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup sysctl_can0pds_values SYSCTL_CAN0PDS Values
|
||||
* @ingroup sysctl_registers
|
||||
* @brief System Control CAN 0 Power Domain Status Register Values
|
||||
@{*/
|
||||
/** Memory Array Power Status Shift */
|
||||
|
|
@ -1303,10 +1266,9 @@
|
|||
#define SYSCTL_CAN0PDS_PWRSTAT_OFF (0x0)
|
||||
/** Power Domain Status - On */
|
||||
#define SYSCTL_CAN0PDS_PWRSTAT_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup sysctl_can0mpc_values SYSCTL_CAN0MPC Values
|
||||
* @ingroup sysctl_registers
|
||||
* @brief System Control CAN 0 Memory Power Control Register Values
|
||||
@{*/
|
||||
/** Memory Array Power Control Shift */
|
||||
|
|
@ -1317,10 +1279,9 @@
|
|||
#define SYSCTL_CAN0MPC_PWRCTL_ARR_OFF (0x0)
|
||||
/** Memory Array Power Control - On */
|
||||
#define SYSCTL_CAN0MPC_PWRCTL_ARR_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup sysctl_can1pds_values SYSCTL_CAN1PDS Values
|
||||
* @ingroup sysctl_registers
|
||||
* @brief System Control CAN 1 Power Domain Status Register Values
|
||||
@{*/
|
||||
/** Memory Array Power Status Shift */
|
||||
|
|
@ -1339,10 +1300,9 @@
|
|||
#define SYSCTL_CAN1PDS_PWRSTAT_OFF (0x0)
|
||||
/** Power Domain Status - On */
|
||||
#define SYSCTL_CAN1PDS_PWRSTAT_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/** @defgroup sysctl_can1mpc_values SYSCTL_CAN1MPC Values
|
||||
* @ingroup sysctl_registers
|
||||
* @brief System Control CAN 1 Memory Power Control Register Values
|
||||
@{*/
|
||||
/** Memory Array Power Control Shift */
|
||||
|
|
@ -1353,7 +1313,7 @@
|
|||
#define SYSCTL_CAN1MPC_PWRCTL_ARR_OFF (0x0)
|
||||
/** Memory Array Power Control - On */
|
||||
#define SYSCTL_CAN1MPC_PWRCTL_ARR_ON (0x3)
|
||||
/*@}*/
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @brief Clock mode definitions
|
||||
|
|
@ -1506,4 +1466,6 @@ void sysctl_periph_set_power_state(enum msp432_power_mode power_mode,
|
|||
|
||||
END_DECLS
|
||||
|
||||
/**@}*/
|
||||
|
||||
#endif /* MSP432E4_SYSTEMCONTROL_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue