From fa47bb80d568f38c09c307f345e2a3ebb04f6a61 Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Tue, 2 Jul 2013 07:45:10 -0400 Subject: [PATCH] lpc43xx/uart: Fix TER register definition I'm not sure why bit 7 and offset 0x30 were used previously. Revision 1.6 of UM10503 claims that the TXEN bit is bit 0 in all UARTs' TER registers. --- include/libopencm3/lpc43xx/uart.h | 8 ++------ lib/lpc43xx/uart.c | 30 ++++++------------------------ 2 files changed, 8 insertions(+), 30 deletions(-) diff --git a/include/libopencm3/lpc43xx/uart.h b/include/libopencm3/lpc43xx/uart.h index 3f3bd354..2fc5fff6 100644 --- a/include/libopencm3/lpc43xx/uart.h +++ b/include/libopencm3/lpc43xx/uart.h @@ -74,9 +74,6 @@ /* Oversampling Register only for UART0/2/3 */ #define UART_OSR(port) MMIO32(port + 0x02C) -/* Transmit Enable Register Only for UART1 */ -#define UART_TER_UART1(port) MMIO32(port + 0x030) - /* Half-Duplex enable Register only for UART0/2/3 */ #define UART_HDEN(port) MMIO32(port + 0x040) @@ -95,7 +92,7 @@ /* Synchronous Mode Control Register only for UART0/2/3 */ #define UART_SYNCCTRL(port) MMIO32(port + 0x058) -/* Transmit Enable Register Only for UART0/2/3 */ +/* Transmit Enable Register */ #define UART_TER(port) MMIO32(port + 0x05C) /* --------------------- BIT DEFINITIONS -------------------------------------- */ @@ -255,8 +252,7 @@ /********************************************************************* * Macro defines for Macro defines for UART Tx Enable register **********************************************************************/ -#define UART1_TER_TXEN ((uint8_t)(BIT7)) /* Transmit enable bit */ -#define UART0_2_3_TER_TXEN ((uint8_t)(BIT0)) /* Transmit enable bit */ +#define UART_TER_TXEN ((uint8_t)(BIT0)) /* Transmit enable bit */ /********************************************************************** * Macro defines for Macro defines for UART FIFO Level register diff --git a/lib/lpc43xx/uart.c b/lib/lpc43xx/uart.c index 44e2a973..b4f90423 100644 --- a/lib/lpc43xx/uart.c +++ b/lib/lpc43xx/uart.c @@ -94,25 +94,13 @@ void uart_init(uart_num_t uart_num, } /* Wait end of TX & disable TX */ - if(uart_num == UART1_NUM) - { - UART_TER_UART1(uart_port) = UART1_TER_TXEN; + UART_TER(uart_port) = UART_TER_TXEN; - /* Wait for current transmit complete */ - while (!(UART_LSR(uart_port) & UART_LSR_THRE)); + /* Wait for current transmit complete */ + while (!(UART_LSR(uart_port) & UART_LSR_THRE)); - /* Disable Tx */ - UART_TER_UART1(uart_port) = 0; - }else - { - UART_TER(uart_port) = UART0_2_3_TER_TXEN; - - /* Wait for current transmit complete */ - while (!(UART_LSR(uart_port) & UART_LSR_THRE)); - - /* Disable Tx */ - UART_TER(uart_port) = 0; - } + /* Disable Tx */ + UART_TER(uart_port) = 0; /* Disable interrupt */ UART_IER(uart_port) = 0; @@ -153,13 +141,7 @@ void uart_init(uart_num_t uart_num, UART_LCR(uart_port) = (lcr_config & UART_LCR_BITMASK); /* Enable TX */ - if(uart_num == UART1_NUM) - { - UART_TER_UART1(uart_port) = UART1_TER_TXEN; - }else - { - UART_TER(uart_port) = UART0_2_3_TER_TXEN; - } + UART_TER(uart_port) = UART_TER_TXEN; } /*