stm32f3: flash_common_f24 now includes f3 support. Also, renamed to f234.
- Makefiles of other stm32s updated accordingly. - f3/rcc.c updated to some definition changes. - f3/flash.c removed in order to use flash_common_f234.c to comply with new organization.
This commit is contained in:
Federico Ruiz Ugalde
Piotr Esden-Tempski
parent
74a313625f
commit
efe08e4898
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@ -40,15 +40,27 @@
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
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#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
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#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
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#if !defined(STM32F3)
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#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#else
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#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
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#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
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#endif
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/* --- FLASH_ACR values ---------------------------------------------------- */
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#if !defined(STM32F3)
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#define FLASH_ACR_DCRST (1 << 12)
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#define FLASH_ACR_ICRST (1 << 11)
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#define FLASH_ACR_DCE (1 << 10)
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#define FLASH_ACR_ICE (1 << 9)
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_PRFTEN (1 << 8)
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#else
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#define FLASH_ACR_PRFTBS (1 << 5)
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#define FLASH_ACR_PRFTBE (1 << 4)
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#define FLASH_ACR_HLFCYA (1 << 3)
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#endif
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#define FLASH_ACR_LATENCY_0WS 0x00
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#define FLASH_ACR_LATENCY_1WS 0x01
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#define FLASH_ACR_LATENCY_2WS 0x02
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@ -60,6 +72,7 @@
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/* --- FLASH_SR values ----------------------------------------------------- */
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#if !defined(STM32F3)
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#define FLASH_SR_BSY (1 << 16)
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#define FLASH_SR_PGSERR (1 << 7)
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#define FLASH_SR_PGPERR (1 << 6)
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@ -67,9 +80,17 @@
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_EOP (1 << 0)
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#else
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_ERLYBSY (1 << 1)
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#define FLASH_SR_PGPERR (1 << 2)
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#define FLASH_SR_WRPRTERR (1 << 4)
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#define FLASH_SR_EOP (1 << 5)
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#endif
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/* --- FLASH_CR values ----------------------------------------------------- */
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#if !defined(STM32F3)
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#define FLASH_CR_LOCK (1 << 31)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_CR_EOPIE (1 << 24)
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@ -93,7 +114,21 @@
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#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
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#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
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#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
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#else
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#define FLASH_CR_OBL_LAUNCH (1 << 13)
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#define FLASH_CR_EOPIE (1 << 12)
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#define FLASH_CR_ERRIE (1 << 10)
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#define FLASH_CR_OPTWRE (1 << 9)
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#define FLASH_CR_LOCK (1 << 7)
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#define FLASH_CR_STRT (1 << 6)
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#define FLASH_CR_OPTER (1 << 5)
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#define FLASH_CR_OPTPG (1 << 4)
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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#endif
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#if !defined(STM32F3)
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/* --- FLASH_OPTCR values -------------------------------------------------- */
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/* FLASH_OPTCR[27:16]: nWRP */
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@ -107,18 +142,35 @@
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#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
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#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
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#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
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#endif
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/* --- FLASH Keys -----------------------------------------------------------*/
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#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
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#if !defined(STM32F3)
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#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)
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#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)
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#endif
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void flash_set_ws(uint32_t ws);
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void flash_unlock(void);
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void flash_lock(void);
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void flash_clear_pgperr_flag(void);
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void flash_clear_eop_flag(void);
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void flash_clear_bsy_flag(void);
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void flash_clear_status_flags(void);
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void flash_wait_for_last_operation(void);
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#if !defined(STM32F3)
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void flash_unlock_option_bytes(void);
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void flash_lock_option_bytes(void);
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void flash_clear_pgserr_flag(void);
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void flash_clear_wrperr_flag(void);
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void flash_clear_pgaerr_flag(void);
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void flash_dcache_enable(void);
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void flash_dcache_disable(void);
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void flash_icache_enable(void);
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@ -127,18 +179,6 @@ void flash_prefetch_enable(void);
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void flash_prefetch_disable(void);
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void flash_dcache_reset(void);
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void flash_icache_reset(void);
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void flash_set_ws(uint32_t ws);
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void flash_unlock(void);
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void flash_lock(void);
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void flash_clear_pgserr_flag(void);
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void flash_clear_pgperr_flag(void);
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void flash_clear_pgaerr_flag(void);
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void flash_clear_eop_flag(void);
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void flash_clear_wrperr_flag(void);
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void flash_clear_bsy_flag(void);
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void flash_clear_status_flags(void);
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void flash_unlock_option_bytes(void);
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void flash_lock_option_bytes(void);
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void flash_erase_all_sectors(uint32_t program_size);
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void flash_erase_sector(uint8_t sector, uint32_t program_size);
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void flash_program_double_word(uint32_t address, uint64_t data);
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@ -146,8 +186,8 @@ void flash_program_word(uint32_t address, uint32_t data);
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void flash_program_half_word(uint32_t address, uint16_t data);
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void flash_program_byte(uint32_t address, uint8_t data);
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void flash_program(uint32_t address, uint8_t *data, uint32_t len);
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void flash_wait_for_last_operation(void);
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void flash_program_option_bytes(uint32_t data);
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#endif
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END_DECLS
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@ -19,7 +19,7 @@
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/flash_common_f24.h>
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#include <libopencm3/stm32/common/flash_common_f234.h>
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#endif
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@ -1,9 +1,6 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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@ -18,107 +15,11 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For details see:
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* PM0081 Programming manual: STM32F30xxx and STM32F31xxx Flash programming
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* September 2011, Doc ID 018520 Rev 1
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* http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/DM00023388.pdf
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- FLASH registers ----------------------------------------------------- */
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#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
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#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
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#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
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#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
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#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
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#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
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/* --- FLASH_ACR values ---------------------------------------------------- */
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#define FLASH_LATENCY_0WS 0x00
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#define FLASH_LATENCY_1WS 0x01
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#define FLASH_LATENCY_2WS 0x02
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#define FLASH_LATENCY_3WS 0x03
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#define FLASH_LATENCY_4WS 0x04
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#define FLASH_LATENCY_5WS 0x05
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#define FLASH_LATENCY_6WS 0x06
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#define FLASH_LATENCY_7WS 0x07
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#define FLASH_PRFTBS (1 << 5)
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#define FLASH_PRFTBE (1 << 4)
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#define FLASH_HLFCYA (1 << 3)
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/* --- FLASH_SR values ----------------------------------------------------- */
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#define FLASH_BSY (1 << 0)
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#define FLASH_ERLYBSY (1 << 1)
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#define FLASH_PGPERR (1 << 2)
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#define FLASH_WRPRTERR (1 << 4)
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#define FLASH_EOP (1 << 5)
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/* --- FLASH_CR values ----------------------------------------------------- */
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#define FLASH_OBL_LAUNCH (1 << 13)
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#define FLASH_EOPIE (1 << 12)
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#define FLASH_ERRIE (1 << 10)
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#define FLASH_OPTWRE (1 << 9)
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#define FLASH_LOCK (1 << 7)
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#define FLASH_STRT (1 << 6)
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#define FLASH_OPTER (1 << 5)
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#define FLASH_OPTPG (1 << 4)
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#define FLASH_MER (1 << 2)
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#define FLASH_PER (1 << 1)
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#define FLASH_PG (1 << 0)
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/* --- FLASH_OBR values ----------------------------------------------------- */
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#define FLASH_OPTERR (1 << 0)
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#define FLASH_RDPRT1 (1 << 1)
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#define FLASH_RDPRT2 (1 << 2)
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#define FLASH_WDG_SW (1 << 8)
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#define FLASH_NRST_STOP (1 << 9)
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#define FLASH_NRST_STDBY (1 << 10)
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#define FLASH_NBOOT1 (1 << 12)
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#define FLASH_VDDA_MONITOR (1 << 13)
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#define FLASH_SRAM_PE (1 << 14)
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/* --- FLASH Keys -----------------------------------------------------------*/
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#define FLASH_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEY2 ((uint32_t)0xcdef89ab)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void flash_set_ws(uint32_t ws);
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void flash_unlock(void);
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void flash_lock(void);
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void flash_clear_pgperr_flag(void);
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void flash_clear_eop_flag(void);
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void flash_clear_bsy_flag(void);
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void flash_clear_status_flags(void);
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/* Functions deactivated, please read flash.c for the reasons */
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/* void flash_erase_all_pages(uint32_t program_size); */
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/* void flash_erase_page(uint32_t page, uint32_t program_size); */
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/* void flash_program_double_word(uint32_t address, uint64_t data, uint32_t program_size); */
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/* void flash_program_word(uint32_t address, uint32_t data, uint32_t program_size); */
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/* void flash_program_half_word(uint32_t address, uint16_t data, uint32_t program_size); */
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/* void flash_program_byte(uint32_t address, uint8_t data, uint32_t program_size); */
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void flash_wait_for_last_operation(void);
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void flash_program_option_bytes(uint32_t data);
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END_DECLS
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#include <libopencm3/stm32/common/flash_common_f234.h>
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#endif
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@ -19,7 +19,7 @@
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/flash_common_f24.h>
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#include <libopencm3/stm32/common/flash_common_f234.h>
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#endif
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@ -21,6 +21,8 @@
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# include <libopencm3/stm32/f1/flash.h>
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#elif defined(STM32F2)
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# include <libopencm3/stm32/f2/flash.h>
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#elif defined(STM32F3)
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# include <libopencm3/stm32/f3/flash.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/flash.h>
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#elif defined(STM32L1)
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@ -20,6 +20,7 @@
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#include <libopencm3/stm32/flash.h>
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#if !defined(STM32F3)
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static inline void flash_set_program_size(uint32_t psize)
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{
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FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
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@ -66,6 +67,24 @@ void flash_icache_reset(void)
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FLASH_ACR |= FLASH_ACR_ICRST;
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}
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void flash_clear_pgserr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGSERR;
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}
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void flash_clear_pgaerr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGAERR;
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}
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void flash_clear_wrperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_WRPERR;
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}
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#endif
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void flash_set_ws(uint32_t ws)
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{
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uint32_t reg32;
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@ -91,31 +110,16 @@ void flash_lock(void)
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FLASH_CR |= FLASH_CR_LOCK;
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}
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void flash_clear_pgserr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGSERR;
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}
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void flash_clear_pgperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGPERR;
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}
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void flash_clear_pgaerr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGAERR;
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}
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void flash_clear_eop_flag(void)
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{
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FLASH_SR |= FLASH_SR_EOP;
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}
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void flash_clear_wrperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_WRPERR;
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}
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void flash_clear_bsy_flag(void)
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{
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FLASH_SR &= ~FLASH_SR_BSY;
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@ -123,14 +127,23 @@ void flash_clear_bsy_flag(void)
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void flash_clear_status_flags(void)
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{
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#if !defined(STM32F3)
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flash_clear_pgserr_flag();
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flash_clear_pgperr_flag();
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flash_clear_pgaerr_flag();
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flash_clear_eop_flag();
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flash_clear_wrperr_flag();
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#endif
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flash_clear_pgperr_flag();
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flash_clear_eop_flag();
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flash_clear_bsy_flag();
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}
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void flash_wait_for_last_operation(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
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}
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#if !defined(STM32F3)
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void flash_unlock_option_bytes(void)
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{
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/* Clear the unlock state. */
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@ -146,11 +159,6 @@ void flash_lock_option_bytes(void)
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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}
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void flash_wait_for_last_operation(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
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}
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void flash_program_double_word(uint32_t address, uint64_t data)
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{
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/* Ensure that all flash operations are complete. */
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@ -267,3 +275,5 @@ void flash_program_option_bytes(uint32_t data)
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FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte prog. */
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flash_wait_for_last_operation();
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}
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#endif
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@ -39,7 +39,7 @@ OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
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gpio_common_all.o gpio_common_f234.o i2c_common_all.o \
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iwdg_common_all.o rtc_common_bcd.o spi_common_all.o \
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timer_common_all.o timer_common_f24.o usart_common_all.o \
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flash_common_f24.o hash_common_f24.o crypto_common_f24.o
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flash_common_f234.o hash_common_f24.o crypto_common_f24.o
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|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
|
|
|
|||
|
|
@ -34,12 +34,12 @@ CFLAGS = -Os -g \
|
|||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
|
||||
OBJS = rcc.o gpio.o flash.o adc.o exti2.o
|
||||
OBJS = rcc.o gpio.o adc.o exti2.o
|
||||
|
||||
OBJS += gpio_common_all.o gpio_common_f234.o i2c_common_all.o\
|
||||
dac_common_all.o usart_common_all.o crc_common_all.o\
|
||||
iwdg_common_all.o spi_common_all.o dma_common_f13.o\
|
||||
timer_common_all.o timer_common_f24.o
|
||||
timer_common_all.o timer_common_f24.o flash_common_f234.o
|
||||
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
|
|
|||
|
|
@ -1,178 +0,0 @@
|
|||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/f3/flash.h>
|
||||
|
||||
/* This function is probably wrong, since deactivated. Please check and fix!
|
||||
static inline void flash_set_program_size(uint32_t psize)
|
||||
{
|
||||
FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
|
||||
FLASH_CR |= psize;
|
||||
}
|
||||
*/
|
||||
|
||||
void flash_set_ws(uint32_t ws)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = FLASH_ACR;
|
||||
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
|
||||
reg32 |= ws;
|
||||
FLASH_ACR = reg32;
|
||||
}
|
||||
|
||||
void flash_unlock(void)
|
||||
{
|
||||
/* Authorize the FPEC access. */
|
||||
FLASH_KEYR = FLASH_KEY1;
|
||||
FLASH_KEYR = FLASH_KEY2;
|
||||
}
|
||||
|
||||
void flash_lock(void)
|
||||
{
|
||||
FLASH_CR |= FLASH_LOCK;
|
||||
}
|
||||
|
||||
void flash_clear_pgperr_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_PGPERR;
|
||||
}
|
||||
|
||||
void flash_clear_eop_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_EOP;
|
||||
}
|
||||
|
||||
void flash_clear_bsy_flag(void)
|
||||
{
|
||||
FLASH_SR &= ~FLASH_BSY;
|
||||
}
|
||||
|
||||
void flash_clear_status_flags(void)
|
||||
{
|
||||
flash_clear_pgperr_flag();
|
||||
flash_clear_eop_flag();
|
||||
flash_clear_bsy_flag();
|
||||
}
|
||||
|
||||
|
||||
void flash_wait_for_last_operation(void)
|
||||
{
|
||||
while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
|
||||
;
|
||||
}
|
||||
|
||||
/* Functions deactivated because flash_set_program_size function may not be */
|
||||
/* working well */
|
||||
/* void flash_program_double_word(uint32_t address, u64 data, uint32_t program_size) */
|
||||
/* { */
|
||||
/* /\* Ensure that all flash operations are complete. *\/ */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* flash_set_program_size(program_size); */
|
||||
|
||||
/* /\* Enable writes to flash. *\/ */
|
||||
/* FLASH_CR |= FLASH_PG; */
|
||||
|
||||
/* /\* Program the first half of the word. *\/ */
|
||||
/* MMIO64(address) = data; */
|
||||
|
||||
/* /\* Wait for the write to complete. *\/ */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
|
||||
/* /\* Disable writes to flash. *\/ */
|
||||
/* FLASH_CR &= ~FLASH_PG; */
|
||||
/* } */
|
||||
|
||||
/* void flash_program_word(uint32_t address, uint32_t data, uint32_t program_size) */
|
||||
/* { */
|
||||
/* /\* Ensure that all flash operations are complete. *\/ */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* flash_set_program_size(program_size); */
|
||||
|
||||
/* /\* Enable writes to flash. *\/ */
|
||||
/* FLASH_CR |= FLASH_PG; */
|
||||
|
||||
/* /\* Program the first half of the word. *\/ */
|
||||
/* MMIO32(address) = data; */
|
||||
|
||||
/* /\* Wait for the write to complete. *\/ */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
|
||||
/* /\* Disable writes to flash. *\/ */
|
||||
/* FLASH_CR &= ~FLASH_PG; */
|
||||
/* } */
|
||||
|
||||
/* void flash_program_half_word(uint32_t address, u16 data, uint32_t program_size) */
|
||||
/* { */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* flash_set_program_size(program_size); */
|
||||
|
||||
/* FLASH_CR |= FLASH_PG; */
|
||||
|
||||
/* MMIO16(address) = data; */
|
||||
|
||||
/* flash_wait_for_last_operation(); */
|
||||
|
||||
/* FLASH_CR &= ~FLASH_PG; /\* Disable the PG bit. *\/ */
|
||||
/* } */
|
||||
|
||||
/* void flash_program_byte(uint32_t address, u8 data, uint32_t program_size) */
|
||||
/* { */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* flash_set_program_size(program_size); */
|
||||
|
||||
/* FLASH_CR |= FLASH_PG; */
|
||||
|
||||
/* MMIO8(address) = data; */
|
||||
|
||||
/* flash_wait_for_last_operation(); */
|
||||
|
||||
/* FLASH_CR &= ~FLASH_PG; /\* Disable the PG bit. *\/ */
|
||||
/* } */
|
||||
|
||||
/* void flash_erase_page(uint32_t page, uint32_t program_size) */
|
||||
/* { */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* flash_set_program_size(program_size); */
|
||||
|
||||
/* FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3); */
|
||||
/* FLASH_CR |= page; */
|
||||
/* FLASH_CR |= FLASH_PER; */
|
||||
/* FLASH_CR |= FLASH_STRT; */
|
||||
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* FLASH_CR &= ~FLASH_PER; */
|
||||
/* FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3); */
|
||||
/* } */
|
||||
|
||||
/* void flash_erase_all_pages(uint32_t program_size) */
|
||||
/* { */
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* flash_set_program_size(program_size); */
|
||||
|
||||
/* FLASH_CR |= FLASH_MER; /\* Enable mass erase. *\/ */
|
||||
/* FLASH_CR |= FLASH_STRT; /\* Trigger the erase. *\/ */
|
||||
|
||||
/* flash_wait_for_last_operation(); */
|
||||
/* FLASH_CR &= ~FLASH_MER; /\* Disable mass erase. *\/ */
|
||||
/* } */
|
||||
|
||||
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ const clock_scale_t hsi_8mhz[CLOCK_END] =
|
|||
.ppre1 = RCC_CFGR_PPRE1_DIV_2,
|
||||
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
|
||||
.power_save = 1,
|
||||
.flash_config = FLASH_PRFTBE | FLASH_LATENCY_2WS,
|
||||
.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS,
|
||||
.apb1_frequency = 22000000,
|
||||
.apb2_frequency = 44000000,
|
||||
},
|
||||
|
|
@ -49,7 +49,7 @@ const clock_scale_t hsi_8mhz[CLOCK_END] =
|
|||
.ppre1 = RCC_CFGR_PPRE1_DIV_2,
|
||||
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
|
||||
.power_save = 1,
|
||||
.flash_config = FLASH_PRFTBE| FLASH_LATENCY_3WS,
|
||||
.flash_config = FLASH_ACR_PRFTBE| FLASH_ACR_LATENCY_3WS,
|
||||
.apb1_frequency = 32000000,
|
||||
.apb2_frequency = 64000000,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
|
|||
gpio_common_all.o gpio_common_f234.o i2c_common_all.o \
|
||||
iwdg_common_all.o pwr_common_all.o rtc_common_bcd.o \
|
||||
spi_common_all.o timer_common_all.o timer_common_f24.o \
|
||||
usart_common_all.o flash_common_f24.o hash_common_f24.o \
|
||||
usart_common_all.o flash_common_f234.o hash_common_f24.o \
|
||||
crypto_common_f24.o
|
||||
|
||||
OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \
|
||||
|
|
|
|||
Loading…
Reference in New Issue