Cleaned up and streamlined DMA support for f1. Definitely needs a bunch of testing!
This commit is contained in:
Piotr Esden-Tempski
parent
20c5e56234
commit
ec904f176b
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@ -90,11 +90,11 @@ int main(void)
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dma_enable_mem2mem_mode(DMA1, DMA_CHANNEL1);
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/* Highest priority. */
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dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR1_PL_VERY_HIGH);
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dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_VERY_HIGH);
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/* 32Bit wide transfer for source and destination. */
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dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR1_MSIZE_32BIT);
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dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR1_PSIZE_32BIT);
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dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_32BIT);
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dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_32BIT);
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/*
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* After every 32bits we have to increase the address because
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@ -2,6 +2,7 @@
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -41,615 +42,225 @@
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#define DMA1_IFCR DMA_IFCR(DMA1)
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#define DMA2_IFCR DMA_IFCR(DMA2)
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/* DMA channel 1 configuration register (DMAx_CCR1) */
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#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0)
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#define DMA1_CCR1 DMA_CCR1(DMA1)
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#define DMA2_CCR1 DMA_CCR1(DMA2)
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/* DMA channel configuration register (DMAx_CCRy) */
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#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \
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(0x14 * ((channel) - 1)))
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/* DMA channel 2 configuration register (DMAx_CCR2) */
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#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1)
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#define DMA1_CCR2 DMA_CCR2(DMA1)
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#define DMA2_CCR2 DMA_CCR2(DMA2)
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#define DMA1_CCR(channel) DMA_CCR(DMA1, channel)
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#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)
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#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)
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#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)
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#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)
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#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)
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#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)
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#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)
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/* DMA channel 3 configuration register (DMAx_CCR3) */
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#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2)
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#define DMA1_CCR3 DMA_CCR3(DMA1)
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#define DMA2_CCR3 DMA_CCR3(DMA2)
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#define DMA2_CCR(channel) DMA_CCR(DMA2, channel)
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#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)
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#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)
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#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)
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#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)
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#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)
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/* DMA channel 4 configuration register (DMAx_CCR4) */
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#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3)
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#define DMA1_CCR4 DMA_CCR4(DMA1)
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#define DMA2_CCR4 DMA_CCR4(DMA2)
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/* DMA number of data register (DMAx_CNDTRy) */
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#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \
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(0x14 * ((channel) - 1)))
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/* DMA channel 5 configuration register (DMAx_CCR5) */
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#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4)
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#define DMA1_CCR5 DMA_CCR5(DMA1)
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#define DMA2_CCR5 DMA_CCR5(DMA2)
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#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)
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#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)
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#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)
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#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)
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#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)
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#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)
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#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)
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#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)
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/* DMA channel 6 configuration register (DMAx_CCR6) */
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#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5)
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#define DMA1_CCR6 DMA_CCR6(DMA1)
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#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)
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#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)
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#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)
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#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)
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#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)
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#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)
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/* DMA channel 7 configuration register (DMAx_CCR7) */
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#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6)
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#define DMA1_CCR7 DMA_CCR7(DMA1)
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/* DMA peripheral address register (DMAx_CPARy) */
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#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \
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(0x14 * ((channel) - 1)))
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/* DMA channel 1 number of data register (DMAx_CNDTR1) */
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#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0)
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#define DMA1_CNDTR1 DMA_CNDTR1(DMA1)
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#define DMA2_CNDTR1 DMA_CNDTR1(DMA2)
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#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)
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#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)
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#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)
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#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)
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#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)
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#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5)
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#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)
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#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)
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/* DMA channel 2 number of data register (DMAx_CNDTR2) */
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#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1)
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#define DMA1_CNDTR2 DMA_CNDTR2(DMA1)
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#define DMA2_CNDTR2 DMA_CNDTR2(DMA2)
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#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)
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#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1)
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#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)
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#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)
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#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)
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#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)
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/* DMA channel 3 number of data register (DMAx_CNDTR3) */
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#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2)
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#define DMA1_CNDTR3 DMA_CNDTR3(DMA1)
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#define DMA2_CNDTR3 DMA_CNDTR3(DMA2)
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/* DMA memory address register (DMAx_CMARy) */
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/* DMA channel 4 number of data register (DMAx_CNDTR4) */
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#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3)
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#define DMA1_CNDTR4 DMA_CNDTR4(DMA1)
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#define DMA2_CNDTR4 DMA_CNDTR4(DMA2)
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#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \
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(0x14 * ((channel) - 1)))
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/* DMA channel 5 number of data register (DMAx_CNDTR5) */
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#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4)
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#define DMA1_CNDTR5 DMA_CNDTR5(DMA1)
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#define DMA2_CNDTR5 DMA_CNDTR5(DMA2)
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#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel)
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#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)
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#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)
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#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)
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#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)
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#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)
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#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)
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#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)
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/* DMA channel 6 number of data register (DMAx_CNDTR6) */
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#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5)
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#define DMA1_CNDTR6 DMA_CNDTR6(DMA1)
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/* DMA channel 7 number of data register (DMAx_CNDTR7) */
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#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6)
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#define DMA1_CNDTR7 DMA_CNDTR7(DMA1)
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/* DMA channel 1 peripheral address register (DMAx_CPAR1) */
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#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0)
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#define DMA1_CPAR1 DMA_CPAR1(DMA1)
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#define DMA2_CPAR1 DMA_CPAR1(DMA2)
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/* DMA channel 2 peripheral address register (DMAx_CPAR2) */
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#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1)
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#define DMA1_CPAR2 DMA_CPAR2(DMA1)
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#define DMA2_CPAR2 DMA_CPAR2(DMA2)
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/* DMA channel 3 peripheral address register (DMAx_CPAR3) */
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#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2)
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#define DMA1_CPAR3 DMA_CPAR3(DMA1)
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#define DMA2_CPAR3 DMA_CPAR3(DMA2)
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/* DMA channel 4 peripheral address register (DMAx_CPAR4) */
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#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3)
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#define DMA1_CPAR4 DMA_CPAR4(DMA1)
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#define DMA2_CPAR4 DMA_CPAR4(DMA2)
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/* DMA channel 5 peripheral address register (DMAx_CPAR5) */
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#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4)
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#define DMA1_CPAR5 DMA_CPAR5(DMA1)
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#define DMA2_CPAR5 DMA_CPAR5(DMA2)
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/* DMA channel 6 peripheral address register (DMAx_CPAR6) */
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#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5)
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#define DMA1_CPAR6 DMA_CPAR6(DMA1)
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/* DMA channel 7 peripheral address register (DMAx_CPAR7) */
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#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6)
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#define DMA1_CPAR7 DMA_CPAR7(DMA1)
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/* DMA channel 1 memory address register (DMAx_CMAR1) */
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#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0)
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#define DMA1_CMAR1 DMA_CMAR1(DMA1)
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#define DMA2_CMAR1 DMA_CMAR1(DMA2)
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/* DMA channel 2 memory address register (DMAx_CMAR2) */
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#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1)
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#define DMA1_CMAR2 DMA_CMAR2(DMA1)
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#define DMA2_CMAR2 DMA_CMAR2(DMA2)
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/* DMA channel 3 memory address register (DMAx_CMAR3) */
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#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2)
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#define DMA1_CMAR3 DMA_CMAR3(DMA1)
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#define DMA2_CMAR3 DMA_CMAR3(DMA2)
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/* DMA channel 4 memory address register (DMAx_CMAR4) */
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#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3)
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#define DMA1_CMAR4 DMA_CMAR4(DMA1)
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#define DMA2_CMAR4 DMA_CMAR4(DMA2)
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/* DMA channel 5 memory address register (DMAx_CMAR5) */
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#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4)
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#define DMA1_CMAR5 DMA_CMAR5(DMA1)
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#define DMA2_CMAR5 DMA_CMAR5(DMA2)
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/* DMA channel 6 memory address register (DMAx_CMAR6) */
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#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5)
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#define DMA1_CMAR6 DMA_CMAR6(DMA1)
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/* DMA channel 7 memory address register (DMAx_CMAR7) */
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#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6)
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#define DMA1_CMAR7 DMA_CMAR7(DMA1)
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#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel)
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#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)
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#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2)
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#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)
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#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)
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#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)
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/* --- DMA_ISR values ------------------------------------------------------ */
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/* TEIF7: Channel 7 transfer error flag */
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#define DMA_ISR_TEIF7 (1 << 27)
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/* HTIF7: Channel 7 half transfer flag */
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#define DMA_ISR_HTIF7 (1 << 26)
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/* TCIF7: Channel 7 transfer complete flag */
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#define DMA_ISR_TCIF7 (1 << 25)
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/* GIF7: Channel 7 global interrupt flag */
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#define DMA_ISR_GIF7 (1 << 24)
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/* TEIF6: Channel 6 transfer error flag */
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#define DMA_ISR_TEIF6 (1 << 23)
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/* HTIF6: Channel 6 half transfer flag */
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#define DMA_ISR_HTIF6 (1 << 22)
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/* TCIF6: Channel 6 transfer complete flag */
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#define DMA_ISR_TCIF6 (1 << 21)
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/* GIF6: Channel 6 global interrupt flag */
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#define DMA_ISR_GIF6 (1 << 20)
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/* TEIF5: Channel 5 transfer error flag */
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#define DMA_ISR_TEIF5 (1 << 19)
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/* HTIF5: Channel 5 half transfer flag */
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#define DMA_ISR_HTIF5 (1 << 18)
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/* TCIF5: Channel 5 transfer complete flag */
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#define DMA_ISR_TCIF5 (1 << 17)
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/* GIF5: Channel 5 global interrupt flag */
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#define DMA_ISR_GIF5 (1 << 16)
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/* TEIF4: Channel 4 transfer error flag */
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#define DMA_ISR_TEIF4 (1 << 15)
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/* HTIF4: Channel 4 half transfer flag */
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#define DMA_ISR_HTIF4 (1 << 14)
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/* TCIF4: Channel 4 transfer complete flag */
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#define DMA_ISR_TCIF4 (1 << 13)
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/* GIF4: Channel 4 global interrupt flag */
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#define DMA_ISR_GIF4 (1 << 12)
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/* TEIF3: Channel 3 transfer error flag */
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#define DMA_ISR_TEIF3 (1 << 11)
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/* HTIF3: Channel 3 half transfer flag */
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#define DMA_ISR_HTIF3 (1 << 10)
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/* TCIF3: Channel 3 transfer complete flag */
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#define DMA_ISR_TCIF3 (1 << 9)
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/* GIF3: Channel 3 global interrupt flag */
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#define DMA_ISR_GIF3 (1 << 8)
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/* TEIF2: Channel 2 transfer error flag */
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#define DMA_ISR_TEIF2 (1 << 7)
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/* HTIF2: Channel 23 half transfer flag */
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#define DMA_ISR_HTIF2 (1 << 6)
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/* TCIF2: Channel 2 transfer complete flag */
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#define DMA_ISR_TCIF2 (1 << 5)
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/* GIF2: Channel 2 global interrupt flag */
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#define DMA_ISR_GIF2 (1 << 4)
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/* TEIF1: Channel 1 transfer error flag */
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#define DMA_ISR_TEIF1 (1 << 3)
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/* HTIF1: Channel 1 half transfer flag */
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#define DMA_ISR_HTIF1 (1 << 2)
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/* TCIF1: Channel 1 transfer complete flag */
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#define DMA_ISR_TCIF1 (1 << 1)
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/* GIF1: Channel 1 global interrupt flag */
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#define DMA_ISR_GIF1 (1 << 0)
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/* TEIF: Transfer error interrupt flag */
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#define DMA_ISR_TEIF_BIT (1 << 3)
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#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF << (4 * (channel) -1))
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#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
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#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
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#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)
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#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)
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#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)
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#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)
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#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
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/* HTIF: Half transfer interrupt flag */
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#define DMA_ISR_HTIF_BIT (1 << 2)
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#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF << (4 * (channel) -1))
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#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
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#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
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#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)
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#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)
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#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5)
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#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6)
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#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
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/* TCIF: Transfer complete interrupt flag */
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#define DMA_ISR_TCIF_BIT (1 << 1)
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#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF << (4 * (channel) -1))
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#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
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#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
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#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)
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#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)
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#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)
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#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)
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#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
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/* GIF: Global interrupt flag */
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#define DMA_ISR_GIF_BIT (1 << 0)
|
||||
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF << (4 * (channel) -1))
|
||||
|
||||
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
|
||||
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
|
||||
#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)
|
||||
#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)
|
||||
#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5)
|
||||
#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)
|
||||
#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)
|
||||
|
||||
/* --- DMA_IFCR values ----------------------------------------------------- */
|
||||
|
||||
/* CTEIF7: Channel 7 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF7 (1 << 27)
|
||||
/* CHTIF7: Channel 7 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF7 (1 << 26)
|
||||
/* CTCIF7: Channel 7 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF7 (1 << 25)
|
||||
/* CGIF7: Channel 7 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF7 (1 << 24)
|
||||
/* CTEIF6: Channel 6 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF6 (1 << 23)
|
||||
/* CHTIF6: Channel 6 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF6 (1 << 22)
|
||||
/* CTCIF6: Channel 6 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF6 (1 << 21)
|
||||
/* CGIF6: Channel 6 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF6 (1 << 20)
|
||||
/* CTEIF5: Channel 5 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF5 (1 << 19)
|
||||
/* CHTIF5: Channel 5 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF5 (1 << 18)
|
||||
/* CTCIF5: Channel 5 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF5 (1 << 17)
|
||||
/* CGIF5: Channel 5 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF5 (1 << 16)
|
||||
/* CTEIF4: Channel 4 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF4 (1 << 15)
|
||||
/* CHTIF4: Channel 4 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF4 (1 << 14)
|
||||
/* CTCIF4: Channel 4 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF4 (1 << 13)
|
||||
/* CGIF4: Channel 4 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF4 (1 << 12)
|
||||
/* CTEIF3: Channel 3 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF3 (1 << 11)
|
||||
/* CHTIF3: Channel 3 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF3 (1 << 10)
|
||||
/* CTCIF3: Channel 3 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF3 (1 << 9)
|
||||
/* CGIF3: Channel 3 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF3 (1 << 8)
|
||||
/* CTEIF2: Channel 2 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF2 (1 << 7)
|
||||
/* CHTIF2: Channel 2 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF2 (1 << 6)
|
||||
/* CTCIF2: Channel 2 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF2 (1 << 5)
|
||||
/* CGIF2: Channel 2 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF2 (1 << 4)
|
||||
/* CTEIF1: Channel 1 transfer error clear */
|
||||
#define DMA_IFCR_CTEIF1 (1 << 3)
|
||||
/* CHTIF1: Channel 1 half transfer clear */
|
||||
#define DMA_IFCR_CHTIF1 (1 << 2)
|
||||
/* CTCIF1: Channel 1 transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF1 (1 << 1)
|
||||
/* CGIF1: Channel 1 global interrupt clear */
|
||||
#define DMA_IFCR_CGIF1 (1 << 0)
|
||||
|
||||
/* --- DMA_CCR1 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR1_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR1_PL_LSB 12
|
||||
#define DMA_CCR1_PL_LOW 0x0
|
||||
#define DMA_CCR1_PL_MEDIUM 0x1
|
||||
#define DMA_CCR1_PL_HIGH 0x2
|
||||
#define DMA_CCR1_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR1_MSIZE_LSB 10
|
||||
#define DMA_CCR1_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR1_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR1_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR1_PSIZE_LSB 8
|
||||
#define DMA_CCR1_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR1_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR1_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR1_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR1_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR1_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR1_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR1_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR1_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR1_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR1_EN (1 << 0)
|
||||
|
||||
/* --- DMA_CCR2 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR2_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR2_PL_LSB 12
|
||||
#define DMA_CCR2_PL_LOW 0x0
|
||||
#define DMA_CCR2_PL_MEDIUM 0x1
|
||||
#define DMA_CCR2_PL_HIGH 0x2
|
||||
#define DMA_CCR2_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR2_MSIZE_LSB 10
|
||||
#define DMA_CCR2_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR2_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR2_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR2_PSIZE_LSB 8
|
||||
#define DMA_CCR2_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR2_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR2_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR2_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR2_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR2_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR2_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR2_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR2_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR2_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR2_EN (1 << 0)
|
||||
|
||||
/* --- DMA_CCR3 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR3_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR3_PL_LSB 12
|
||||
#define DMA_CCR3_PL_LOW 0x0
|
||||
#define DMA_CCR3_PL_MEDIUM 0x1
|
||||
#define DMA_CCR3_PL_HIGH 0x2
|
||||
#define DMA_CCR3_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR3_MSIZE_LSB 10
|
||||
#define DMA_CCR3_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR31_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR3_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR3_PSIZE_LSB 8
|
||||
#define DMA_CCR3_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR3_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR3_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR3_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR3_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR3_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR3_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR3_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR3_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR3_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR3_EN (1 << 0)
|
||||
|
||||
/* --- DMA_CCR4 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR4_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR4_PL_LSB 12
|
||||
#define DMA_CCR4_PL_LOW 0x0
|
||||
#define DMA_CCR4_PL_MEDIUM 0x1
|
||||
#define DMA_CCR4_PL_HIGH 0x2
|
||||
#define DMA_CCR4_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR4_MSIZE_LSB 10
|
||||
#define DMA_CCR4_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR4_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR4_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR4_PSIZE_LSB 8
|
||||
#define DMA_CCR4_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR4_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR4_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR4_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR4_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR4_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR4_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR4_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR4_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR4_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR4_EN (1 << 0)
|
||||
|
||||
/* --- DMA_CCR5 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR5_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR5_PL_LSB 12
|
||||
#define DMA_CCR5_PL_LOW 0x0
|
||||
#define DMA_CCR5_PL_MEDIUM 0x1
|
||||
#define DMA_CCR5_PL_HIGH 0x2
|
||||
#define DMA_CCR5_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR5_MSIZE_LSB 10
|
||||
#define DMA_CCR5_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR5_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR5_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR5_PSIZE_LSB 8
|
||||
#define DMA_CCR5_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR5_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR5_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR5_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR5_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR5_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR5_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR5_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR5_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR5_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR5_EN (1 << 0)
|
||||
|
||||
/* --- DMA_CCR6 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR6_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR6_PL_LSB 12
|
||||
#define DMA_CCR6_PL_LOW 0x0
|
||||
#define DMA_CCR6_PL_MEDIUM 0x1
|
||||
#define DMA_CCR6_PL_HIGH 0x2
|
||||
#define DMA_CCR6_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR6_MSIZE_LSB 10
|
||||
#define DMA_CCR6_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR6_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR6_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR6_PSIZE_LSB 8
|
||||
#define DMA_CCR6_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR6_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR6_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR6_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR6_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR6_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR6_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR6_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR6_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR6_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR6_EN (1 << 0)
|
||||
|
||||
/* --- DMA_CCR7 values ----------------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR7_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR7_PL_LSB 12
|
||||
#define DMA_CCR7_PL_LOW 0x0
|
||||
#define DMA_CCR7_PL_MEDIUM 0x1
|
||||
#define DMA_CCR7_PL_HIGH 0x2
|
||||
#define DMA_CCR7_PL_VERY_HIGH 0x3
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR7_MSIZE_LSB 10
|
||||
#define DMA_CCR7_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR7_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR7_MSIZE_32BIT 0x2
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR7_PSIZE_LSB 8
|
||||
#define DMA_CCR7_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR7_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR7_PSIZE_32BIT 0x2
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR7_MINC (1 << 7)
|
||||
|
||||
/* PINC: Peripheral increment mode */
|
||||
#define DMA_CCR7_PINC (1 << 6)
|
||||
|
||||
/* CIRC: Circular mode */
|
||||
#define DMA_CCR7_CIRC (1 << 5)
|
||||
|
||||
/* DIR: Data transfer direction */
|
||||
#define DMA_CCR7_DIR (1 << 4)
|
||||
|
||||
/* TEIE: Transfer error interrupt enable */
|
||||
#define DMA_CCR7_TEIE (1 << 3)
|
||||
|
||||
/* HTIE: Half transfer interrupt enable */
|
||||
#define DMA_CCR7_HTIE (1 << 2)
|
||||
|
||||
/* TCIE: Transfer complete interrupt enable */
|
||||
#define DMA_CCR7_TCIE (1 << 1)
|
||||
|
||||
/* EN: Channel enable */
|
||||
#define DMA_CCR7_EN (1 << 0)
|
||||
/* CTEIF: Transfer error clear */
|
||||
#define DMA_IFCR_CTEIF_BIT (1 << 3)
|
||||
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * (channel) -1))
|
||||
|
||||
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
|
||||
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)
|
||||
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)
|
||||
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)
|
||||
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)
|
||||
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
|
||||
|
||||
/* CHTIF: Half transfer clear */
|
||||
#define DMA_IFCR_CHTIF_BIT (1 << 2)
|
||||
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * (channel) -1))
|
||||
|
||||
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
|
||||
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)
|
||||
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)
|
||||
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)
|
||||
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)
|
||||
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
|
||||
|
||||
/* CTCIF: Transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF_BIT (1 << 1)
|
||||
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * (channel) -1))
|
||||
|
||||
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
|
||||
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)
|
||||
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4)
|
||||
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)
|
||||
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)
|
||||
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
|
||||
|
||||
/* CGIF: Global interrupt clear */
|
||||
#define DMA_IFCR_CGIF_BIT (1 << 0)
|
||||
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * (channel) -1))
|
||||
|
||||
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
|
||||
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)
|
||||
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)
|
||||
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)
|
||||
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)
|
||||
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)
|
||||
|
||||
/* Clear interrupts mask */
|
||||
#define DMA_IFCR_CIF_BIT 0xF
|
||||
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (4 * ((channel) - 1)))
|
||||
|
||||
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
|
||||
#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)
|
||||
#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)
|
||||
#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)
|
||||
#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)
|
||||
#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)
|
||||
|
||||
/* --- DMA_CCRx generic values --------------------------------------------- */
|
||||
|
||||
/* MEM2MEM: Memory to memory mode */
|
||||
#define DMA_CCR_MEM2MEM (1 << 14)
|
||||
#define DMA_CCR_MEM2MEM (1 << 14)
|
||||
|
||||
/* PL[13:12]: Channel priority level */
|
||||
#define DMA_CCR_PL_LSB 12
|
||||
#define DMA_CCR_PL_LOW 0x0
|
||||
#define DMA_CCR_PL_MEDIUM 0x1
|
||||
#define DMA_CCR_PL_HIGH 0x2
|
||||
#define DMA_CCR_PL_VERY_HIGH 0x3
|
||||
#define DMA_CCR_PL_LOW (0x0 << 12)
|
||||
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
|
||||
#define DMA_CCR_PL_HIGH (0x2 << 12)
|
||||
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
|
||||
#define DMA_CCR_PL_MASK (0x3 << 12)
|
||||
#define DMA_CCR_PL_SHIFT 12
|
||||
|
||||
/* MSIZE[11:10]: Memory size */
|
||||
#define DMA_CCR_MSIZE_LSB 10
|
||||
#define DMA_CCR_MSIZE_8BIT 0x0
|
||||
#define DMA_CCR_MSIZE_16BIT 0x1
|
||||
#define DMA_CCR_MSIZE_32BIT 0x2
|
||||
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
|
||||
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
|
||||
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
|
||||
#define DMA_CCR_MSIZE_MASK (0x2 << 10)
|
||||
#define DMA_CCR_MSIZE_SHIFT 10
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_LSB 8
|
||||
#define DMA_CCR_PSIZE_8BIT 0x0
|
||||
#define DMA_CCR_PSIZE_16BIT 0x1
|
||||
#define DMA_CCR_PSIZE_32BIT 0x2
|
||||
#define DMA_CCR_PSIZE_8BIT (0x0 << 10)
|
||||
#define DMA_CCR_PSIZE_16BIT (0x1 << 10)
|
||||
#define DMA_CCR_PSIZE_32BIT (0x2 << 10)
|
||||
#define DMA_CCR_PSIZE_MASK (0x2 << 10)
|
||||
#define DMA_CCR_PSIZE_SHIFT 8
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
#define DMA_CCR_MINC (1 << 7)
|
||||
|
|
@ -700,9 +311,9 @@
|
|||
/* --- function prototypes ------------------------------------------------- */
|
||||
|
||||
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
|
||||
void dma_set_priority(u32 dma, u8 channel, u8 prio);
|
||||
void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size);
|
||||
void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size);
|
||||
void dma_set_priority(u32 dma, u8 channel, u32 prio);
|
||||
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
|
||||
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
|
||||
void dma_enable_memory_increment_mode(u32 dma, u8 channel);
|
||||
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
|
||||
void dma_enable_circular_mode(u32 dma, u8 channel);
|
||||
|
|
|
|||
|
|
@ -19,498 +19,124 @@
|
|||
|
||||
#include <libopencm3/stm32/f1/dma.h>
|
||||
|
||||
void dma_channel_reset(u32 dma, u8 channel)
|
||||
{
|
||||
/* Disable channel. */
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
|
||||
/* Reset config bits. */
|
||||
DMA_CCR(dma, channel) = 0;
|
||||
/* Reset data transfer number. */
|
||||
DMA_CNDTR(dma, channel) = 0;
|
||||
/* Reset peripheral address. */
|
||||
DMA_CPAR(dma, channel) = 0;
|
||||
/* Reset memory address. */
|
||||
DMA_CMAR(dma, channel) = 0;
|
||||
/* Reset interrupt flags. */
|
||||
DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
|
||||
}
|
||||
|
||||
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM;
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_CIRC;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_MEM2MEM;
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_CIRC;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_MEM2MEM;
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_CIRC;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_MEM2MEM;
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_CIRC;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_MEM2MEM;
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_CIRC;
|
||||
case 6:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR6(dma) |= DMA_CCR6_MEM2MEM;
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_CIRC;
|
||||
}
|
||||
case 7:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR7(dma) |= DMA_CCR7_MEM2MEM;
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_CIRC;
|
||||
}
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
|
||||
}
|
||||
|
||||
void dma_set_priority(u32 dma, u8 channel, u8 prio)
|
||||
void dma_set_priority(u32 dma, u8 channel, u32 prio)
|
||||
{
|
||||
if (prio > 3)
|
||||
return;
|
||||
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB);
|
||||
DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB);
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PL_LSB);
|
||||
DMA_CCR2(dma) |= (prio << DMA_CCR2_PL_LSB);
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PL_LSB);
|
||||
DMA_CCR3(dma) |= (prio << DMA_CCR3_PL_LSB);
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PL_LSB);
|
||||
DMA_CCR4(dma) |= (prio << DMA_CCR4_PL_LSB);
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PL_LSB);
|
||||
DMA_CCR5(dma) |= (prio << DMA_CCR5_PL_LSB);
|
||||
case 6:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PL_LSB);
|
||||
DMA_CCR6(dma) |= (prio << DMA_CCR6_PL_LSB);
|
||||
}
|
||||
case 7:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PL_LSB);
|
||||
DMA_CCR7(dma) |= (prio << DMA_CCR7_PL_LSB);
|
||||
}
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
|
||||
DMA_CCR(dma, channel) |= prio;
|
||||
}
|
||||
|
||||
void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size)
|
||||
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
|
||||
{
|
||||
if (mem_size > 2)
|
||||
return;
|
||||
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB);
|
||||
DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB);
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_MSIZE_LSB);
|
||||
DMA_CCR2(dma) |= (mem_size << DMA_CCR2_MSIZE_LSB);
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_MSIZE_LSB);
|
||||
DMA_CCR3(dma) |= (mem_size << DMA_CCR3_MSIZE_LSB);
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_MSIZE_LSB);
|
||||
DMA_CCR4(dma) |= (mem_size << DMA_CCR4_MSIZE_LSB);
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_MSIZE_LSB);
|
||||
DMA_CCR5(dma) |= (mem_size << DMA_CCR5_MSIZE_LSB);
|
||||
case 6:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_MSIZE_LSB);
|
||||
DMA_CCR6(dma) |= (mem_size << DMA_CCR6_MSIZE_LSB);
|
||||
}
|
||||
case 7:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_MSIZE_LSB);
|
||||
DMA_CCR7(dma) |= (mem_size << DMA_CCR7_MSIZE_LSB);
|
||||
}
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
|
||||
DMA_CCR(dma, channel) |= mem_size;
|
||||
}
|
||||
|
||||
void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size)
|
||||
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
|
||||
{
|
||||
if (peripheral_size > 2)
|
||||
return;
|
||||
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB);
|
||||
DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB);
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PSIZE_LSB);
|
||||
DMA_CCR2(dma) |= (peripheral_size << DMA_CCR2_PSIZE_LSB);
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PSIZE_LSB);
|
||||
DMA_CCR3(dma) |= (peripheral_size << DMA_CCR3_PSIZE_LSB);
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PSIZE_LSB);
|
||||
DMA_CCR4(dma) |= (peripheral_size << DMA_CCR4_PSIZE_LSB);
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PSIZE_LSB);
|
||||
DMA_CCR5(dma) |= (peripheral_size << DMA_CCR5_PSIZE_LSB);
|
||||
case 6:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB);
|
||||
DMA_CCR6(dma) |=
|
||||
(peripheral_size << DMA_CCR6_PSIZE_LSB);
|
||||
}
|
||||
case 7:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB);
|
||||
DMA_CCR7(dma) |=
|
||||
(peripheral_size << DMA_CCR7_PSIZE_LSB);
|
||||
}
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
|
||||
DMA_CCR(dma, channel) |= peripheral_size;
|
||||
}
|
||||
|
||||
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_MINC;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_MINC;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_MINC;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_MINC;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_MINC;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_MINC;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_MINC;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
|
||||
}
|
||||
|
||||
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_PINC;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_PINC;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_PINC;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_PINC;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_PINC;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_PINC;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_PINC;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
|
||||
}
|
||||
|
||||
void dma_enable_circular_mode(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_CIRC;
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_CIRC;
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_MEM2MEM;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_CIRC;
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_MEM2MEM;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_CIRC;
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_MEM2MEM;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_CIRC;
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_MEM2MEM;
|
||||
case 6:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR6(dma) |= DMA_CCR6_CIRC;
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_MEM2MEM;
|
||||
}
|
||||
case 7:
|
||||
if (dma == DMA1) {
|
||||
DMA_CCR7(dma) |= DMA_CCR7_CIRC;
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_MEM2MEM;
|
||||
}
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
|
||||
}
|
||||
|
||||
void dma_set_read_from_peripheral(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_DIR;
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_DIR;
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_DIR;
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_DIR;
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_DIR;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_DIR;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_DIR;
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
|
||||
}
|
||||
|
||||
void dma_set_read_from_memory(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_DIR;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_DIR;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_DIR;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_DIR;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_DIR;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_DIR;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_DIR;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
|
||||
}
|
||||
|
||||
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_TEIE;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_TEIE;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_TEIE;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_TEIE;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_TEIE;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_TEIE;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_TEIE;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
|
||||
}
|
||||
|
||||
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_TEIE;
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_TEIE;
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_TEIE;
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_TEIE;
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_TEIE;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_TEIE;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_TEIE;
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
|
||||
}
|
||||
|
||||
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_HTIE;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_HTIE;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_HTIE;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_HTIE;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_HTIE;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_HTIE;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_HTIE;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
|
||||
}
|
||||
|
||||
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_HTIE;
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_HTIE;
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_HTIE;
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_HTIE;
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_HTIE;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_HTIE;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_HTIE;
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
|
||||
}
|
||||
|
||||
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_TCIE;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_TCIE;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_TCIE;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_TCIE;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_TCIE;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_TCIE;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_TCIE;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
|
||||
}
|
||||
|
||||
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_TCIE;
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_TCIE;
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_TCIE;
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_TCIE;
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_TCIE;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_TCIE;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_TCIE;
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
|
||||
}
|
||||
|
||||
void dma_enable_channel(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) |= DMA_CCR1_EN;
|
||||
case 2:
|
||||
DMA_CCR2(dma) |= DMA_CCR2_EN;
|
||||
case 3:
|
||||
DMA_CCR3(dma) |= DMA_CCR3_EN;
|
||||
case 4:
|
||||
DMA_CCR4(dma) |= DMA_CCR4_EN;
|
||||
case 5:
|
||||
DMA_CCR5(dma) |= DMA_CCR5_EN;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) |= DMA_CCR6_EN;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) |= DMA_CCR7_EN;
|
||||
}
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_EN;
|
||||
}
|
||||
|
||||
void dma_disable_channel(u32 dma, u8 channel)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CCR1(dma) &= ~DMA_CCR1_EN;
|
||||
case 2:
|
||||
DMA_CCR2(dma) &= ~DMA_CCR2_EN;
|
||||
case 3:
|
||||
DMA_CCR3(dma) &= ~DMA_CCR3_EN;
|
||||
case 4:
|
||||
DMA_CCR4(dma) &= ~DMA_CCR4_EN;
|
||||
case 5:
|
||||
DMA_CCR5(dma) &= ~DMA_CCR5_EN;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR6(dma) &= ~DMA_CCR6_EN;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CCR7(dma) &= ~DMA_CCR7_EN;
|
||||
}
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
|
||||
}
|
||||
|
||||
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CPAR1(dma) = (u32) address;
|
||||
case 2:
|
||||
DMA_CPAR2(dma) = (u32) address;
|
||||
case 3:
|
||||
DMA_CPAR3(dma) = (u32) address;
|
||||
case 4:
|
||||
DMA_CPAR4(dma) = (u32) address;
|
||||
case 5:
|
||||
DMA_CPAR5(dma) = (u32) address;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CPAR6(dma) = (u32) address;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CPAR7(dma) = (u32) address;
|
||||
}
|
||||
DMA_CPAR(dma, channel) = (u32) address;
|
||||
}
|
||||
|
||||
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CMAR1(dma) = (u32) address;
|
||||
case 2:
|
||||
DMA_CMAR2(dma) = (u32) address;
|
||||
case 3:
|
||||
DMA_CMAR3(dma) = (u32) address;
|
||||
case 4:
|
||||
DMA_CMAR4(dma) = (u32) address;
|
||||
case 5:
|
||||
DMA_CMAR5(dma) = (u32) address;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CMAR6(dma) = (u32) address;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CMAR7(dma) = (u32) address;
|
||||
}
|
||||
DMA_CMAR(dma, channel) = (u32) address;
|
||||
}
|
||||
|
||||
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
|
||||
{
|
||||
switch (channel) {
|
||||
case 1:
|
||||
DMA_CNDTR1(dma) = number;
|
||||
case 2:
|
||||
DMA_CNDTR2(dma) = number;
|
||||
case 3:
|
||||
DMA_CNDTR3(dma) = number;
|
||||
case 4:
|
||||
DMA_CNDTR4(dma) = number;
|
||||
case 5:
|
||||
DMA_CNDTR5(dma) = number;
|
||||
case 6:
|
||||
if (dma == DMA1)
|
||||
DMA_CNDTR6(dma) = number;
|
||||
case 7:
|
||||
if (dma == DMA1)
|
||||
DMA_CNDTR7(dma) = number;
|
||||
}
|
||||
DMA_CNDTR(dma, channel) = number;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue