Factored out CAN helper functions out of the example. Test code now also uses the received data.
This commit is contained in:
Piotr Esden-Tempski
parent
c6e86901e8
commit
e7d765ea90
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@ -88,8 +88,6 @@ void systick_setup()
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void can_setup()
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{
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u32 wait_ack = 0x00000000;
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u32 can_msr_inak_timeout = 0x000FFFFF;
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/* Enable peripheral clocks */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
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@ -109,156 +107,111 @@ void can_setup()
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nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);
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nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1);
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/* --- reset CAN periphery ------------------------------------------ */
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/* reset CAN */
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can_reset(CAN1);
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CANRST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CANRST);
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/* CAN cell init */
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if (can_init(CAN1,
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false, /* TTCM: Time triggered comm mode? */
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true, /* ABOM: Automatic bus-off management? */
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false, /* AWUM: Automatic wakeup mode? */
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false, /* NART: No automatic retransmission? */
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false, /* RFLM: Receive FIFO locked mode? */
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false, /* TXFP: Transmit FIFO priority? */
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CAN_BTR_SJW_1TQ,
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CAN_BTR_TS1_3TQ,
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CAN_BTR_TS2_4TQ,
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12)) { /* BRP+1: Baud rate prescaler */
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/* --- CAN cell init ------------------------------------------------ */
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gpio_set(GPIOA, GPIO6); /* LED0 off */
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gpio_set(GPIOA, GPIO7); /* LED1 off */
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gpio_set(GPIOB, GPIO0); /* LED2 off */
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gpio_clear(GPIOB, GPIO1); /* LED3 on */
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/* Exit from sleep mode */
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CAN_MCR(CAN1) &= ~CAN_MCR_SLEEP;
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/* Request initialization "enter" */
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CAN_MCR(CAN1) |= CAN_MCR_INRQ;
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/* Wait for acknowledge */
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while ((wait_ack != can_msr_inak_timeout) &&
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((CAN_MSR(CAN1) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
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wait_ack++;
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}
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/* Check the acknowledge */
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if ((CAN_MSR(CAN1) & CAN_MSR_INAK) != CAN_MSR_INAK) {
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/* we should set some flag here or so because we failed */
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gpio_clear(GPIOB, GPIO1);
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} else {
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/* set the automatic bus-off management */
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CAN_MCR(CAN1) &= ~CAN_MCR_TTCM;
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CAN_MCR(CAN1) |= CAN_MCR_ABOM;
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CAN_MCR(CAN1) &= ~CAN_MCR_AWUM;
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CAN_MCR(CAN1) &= ~CAN_MCR_NART;
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CAN_MCR(CAN1) &= ~CAN_MCR_TXFP;
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/* Set bit timings */
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CAN_BTR(CAN1) = 0x00000000 |
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CAN_BTR_SJW_1TQ |
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CAN_BTR_TS2_4TQ |
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CAN_BTR_TS1_3TQ |
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(u32)(CAN_BTR_BRP_MASK & (12 - 1));
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/* Request initialization "leave" */
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CAN_MCR(CAN1) &= ~CAN_MCR_INRQ;
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/* Wait for acknowledge */
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wait_ack = 0x00000000;
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while ((wait_ack != can_msr_inak_timeout) &&
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((CAN_MSR(CAN1) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
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wait_ack++;
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}
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if ((CAN_MSR(CAN1) & CAN_MSR_INAK) == CAN_MSR_INAK) {
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/* set some flag here because we failed */
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gpio_clear(GPIOB, GPIO1);
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} else {
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/* set some flag here because we succeeded */
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gpio_set(GPIOB, GPIO1);
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/* die because we failed to initialize */
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while(1){
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__asm("nop");
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}
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}
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/* --- CAN filter 0 init -------------------------------------------- */
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u32 filter_select_bit = 0x00000001;
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/* Request initialization "enter" */
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CAN_FMR(CAN1) |= CAN_FMR_FINIT;
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/* Deactivate the filter */
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CAN_FA1R(CAN1) &= ~filter_select_bit;
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/* Set 32-bit scale for the filter */
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CAN_FS1R(CAN1) |= filter_select_bit;
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/* Set the filter id to 0 */
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CAN_FiR1(CAN1, 0) = 0x00000000;
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/* Set the filter id mask to 0 */
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CAN_FiR2(CAN1, 0) = 0x00000000;
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/* Set filter mode to Id/Mask mode */
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CAN_FM1R(CAN1) &= ~filter_select_bit;
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/* Select FIFO0 as filter assignement */
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CAN_FFA1R(CAN1) &= ~filter_select_bit;
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/* Reactivate the filter */
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CAN_FA1R(CAN1) |= filter_select_bit;
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/* Request initialization "leave" */
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CAN_FMR(CAN1) &= ~CAN_FMR_FINIT;
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can_filter_id_mask_32bit_init(CAN1,
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0, /* Filter id */
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0, /* CAN id */
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0, /* CAN id mask */
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0, /* FIFO assignement (in this case FIFO0) */
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true); /* Enable the filter */
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/* --- Enable CAN rx interrupt -------------------------------------- */
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CAN_IER(CAN1) |= CAN_IER_FMPIE0;
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}
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void can_transmit(u32 id, u8 length, u8 data)
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{
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u32 mailbox = 0;
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if ((CAN_TSR(CAN1) & CAN_TSR_TME0) == CAN_TSR_TME0) {
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mailbox = CAN_MBOX0;
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gpio_set(GPIOB, GPIO0);
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} else if ((CAN_TSR(CAN1) & CAN_TSR_TME1) == CAN_TSR_TME1) {
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mailbox = CAN_MBOX1;
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gpio_set(GPIOB, GPIO0);
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} else if ((CAN_TSR(CAN1) & CAN_TSR_TME2) == CAN_TSR_TME2) {
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mailbox = CAN_MBOX2;
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gpio_set(GPIOB, GPIO0);
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} else {
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mailbox = 0; /* no mailbox */
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gpio_clear(GPIOB, GPIO0);
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}
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if ( mailbox != 0 ) { /* check if we have an empty mailbox */
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/* Set the ID */
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CAN_TIxR(CAN1, mailbox) |= id << CAN_TIxR_STID_SHIFT;
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/* Set the DLC */
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CAN_TDTxR(CAN1, mailbox) &= 0xFFFFFFFF0;
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CAN_TDTxR(CAN1, mailbox) |= length & CAN_TDTxR_DLC_MASK;
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/* Set the data */
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CAN_TDLxR(CAN1, mailbox) = data;
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CAN_TDHxR(CAN1, mailbox) = 0x00000000;
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/* Request transmission */
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CAN_TIxR(CAN1, mailbox) |= CAN_TIxR_TXRQ;
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}
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can_enable_irq(CAN1, CAN_IER_FMPIE0);
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}
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void sys_tick_handler()
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{
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static int temp32 = 0;
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static u8 data[8] = {0,1,2,0,0,0,0,0};
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temp32++;
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/* we call this handler every 1ms so 1000ms = 1s on/off */
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if (temp32 == 1000) {
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gpio_toggle(GPIOA, GPIO6); /* LED2 on/off */
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temp32 = 0;
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/* --- Transmit CAN frame ----------------------------------- */
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can_transmit(0, 0, 10);
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data[0]++;
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if(can_transmit(CAN1,
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0, /* (EX/ST)ID: CAN id */
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false, /* IDE: CAN id extended? */
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false, /* RTR: Request Transmit? */
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8, /* DLC: Data Length */
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data) == -1) {
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gpio_set(GPIOA, GPIO6); /* LED0 off */
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gpio_set(GPIOA, GPIO7); /* LED1 off */
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gpio_clear(GPIOB, GPIO0); /* LED2 on */
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gpio_set(GPIOB, GPIO1); /* LED3 off */
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}
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}
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}
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void usb_lp_can_rx0_isr(void)
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{
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gpio_toggle(GPIOA, GPIO7);
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CAN_RF0R(CAN1) |= CAN_RF0R_RFOM0;
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u32 id;
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bool ext;
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bool rtr;
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u32 fmi;
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u8 length;
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u8 data[8];
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can_receive(CAN1, 0, false, &id, &ext, &rtr, &fmi, &length, data);
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if (data[0] & 1) {
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gpio_clear(GPIOA, GPIO6);
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} else {
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gpio_set(GPIOA, GPIO6);
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}
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if (data[0] & 2) {
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gpio_clear(GPIOA, GPIO7);
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} else {
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gpio_set(GPIOA, GPIO7);
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}
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if (data[0] & 4) {
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gpio_clear(GPIOB, GPIO0);
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} else {
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gpio_set(GPIOB, GPIO0);
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}
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if (data[0] & 8) {
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gpio_clear(GPIOB, GPIO1);
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} else {
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gpio_set(GPIOB, GPIO1);
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}
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can_fifo_release(CAN1, 0);
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}
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int main(void)
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@ -528,10 +528,9 @@
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#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
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#define CAN_RDTxR_TIME_SHIFT 15
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/* 15:6 Reserved, forced by hardware to 0 */
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/* TGT: Transmit global time */
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#define CAN_RDTxR_TGT (1 << 5)
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/* FMI[7:0]: Filter match index */
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#define CAN_RDTxR_FMI_MASK (0xFF << 8)
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#define CAN_RDTxR_FMI_SHIFT 8
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/* 7:4 Reserved, forced by hardware to 0 */
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@ -607,4 +606,42 @@
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/* FB[31:0]: Filter bits */
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/* --- CAN functions -------------------------------------------------------- */
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void can_reset(u32 canport);
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int can_init(u32 canport,
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bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp,
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u32 sjw, u32 ts1, u32 ts2, u32 brp);
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void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
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u32 fr1, u32 fr2,
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u32 fifo, bool enable);
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void can_filter_id_mask_16bit_init(u32 canport, u32 nr,
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u16 id1, u16 mask1,
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u16 id2, u16 mask2,
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u32 fifo, bool enable);
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void can_filter_id_mask_32bit_init(u32 canport, u32 nr,
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u32 id, u32 mask,
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u32 fifo, bool enable);
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void can_filter_id_list_16bit_init(u32 canport, u32 nr,
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u16 id1, u16 id2,
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u16 id3, u16 id4,
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u32 fifo, bool enable);
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void can_filter_id_list_32bit_init(u32 canport, u32 nr,
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u32 id1, u32 id2,
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u32 fifo, bool enable);
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void can_enable_irq(u32 canport, u32 irq);
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void can_disable_irq(u32 canport, u32 irq);
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int can_transmit(u32 canport, u32 id,
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bool ext, bool rtr,
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u8 length, u8 *data);
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void can_receive(u32 canport, u8 fifo, bool release,
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u32 *id, bool *ext, bool *rtr, u32 *fmi,
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u8 *length, u8 *data);
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void can_fifo_release(u32 canport, u8 fifo);
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#endif /* LIBOPENSTM32_CAN_H */
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@ -21,6 +21,7 @@
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#define LIBOPENSTM32_COMMON_H
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#include <stdint.h>
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#include <stdbool.h>
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/* Type definitions for shorter and nicer code */
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typedef int8_t s8;
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@ -29,7 +29,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../include -fno-common \
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ARFLAGS = rcs
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OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
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rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
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usb_f103.o usb.o usb_control.o usb_standard.o
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usb_f103.o usb.o usb_control.o usb_standard.o can.o
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VPATH += usb
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@ -0,0 +1,352 @@
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/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopenstm32/can.h>
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#include <libopenstm32/rcc.h>
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void can_reset(u32 canport)
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{
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if(canport == CAN1){
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
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}else{
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
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}
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}
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int can_init(u32 canport,
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bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp,
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u32 sjw, u32 ts1, u32 ts2, u32 brp)
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{
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u32 wait_ack = 0x00000000;
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u32 can_msr_inak_timeout = 0x0000FFFF;
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int ret = 0;
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/* Exit from sleep mode */
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CAN_MCR(canport) &= ~CAN_MCR_SLEEP;
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/* Request initialization "enter" */
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CAN_MCR(canport) |= CAN_MCR_INRQ;
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/* Wait for acknowledge */
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while ((wait_ack != can_msr_inak_timeout) &&
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((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
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wait_ack++;
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}
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/* Check the acknowledge */
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if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) {
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ret = 1;
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} else {
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/* set the automatic bus-off management */
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if (ttcm) {
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CAN_MCR(canport) |= CAN_MCR_TTCM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_TTCM;
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}
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if (abom) {
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CAN_MCR(canport) |= CAN_MCR_ABOM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_ABOM;
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}
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if (awum) {
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CAN_MCR(canport) |= CAN_MCR_AWUM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_AWUM;
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}
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if (nart) {
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CAN_MCR(canport) |= CAN_MCR_NART;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_NART;
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}
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if (rflm) {
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CAN_MCR(canport) |= CAN_MCR_RFLM;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_RFLM;
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}
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if (txfp) {
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CAN_MCR(canport) |= CAN_MCR_TXFP;
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} else {
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CAN_MCR(canport) &= ~CAN_MCR_TXFP;
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}
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/* Set bit timings */
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CAN_BTR(canport) = sjw |
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ts2 |
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ts1 |
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(u32)(CAN_BTR_BRP_MASK & (brp - 1));
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/* Request initialization "leave" */
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CAN_MCR(canport) &= ~CAN_MCR_INRQ;
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/* Wait for acknowledge */
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wait_ack = 0x00000000;
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while ((wait_ack != can_msr_inak_timeout) &&
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((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
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wait_ack++;
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}
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if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) {
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ret = 1;
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}
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}
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return ret;
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}
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void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
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u32 fr1, u32 fr2,
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u32 fifo, bool enable)
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{
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u32 filter_select_bit = 0x00000001 << nr;
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/* Request initialization "enter" */
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CAN_FMR(canport) |= CAN_FMR_FINIT;
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/* Deactivate the filter */
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CAN_FA1R(canport) &= ~filter_select_bit;
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if (scale_32bit) {
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/* Set 32-bit scale for the filter */
|
||||
CAN_FS1R(canport) |= filter_select_bit;
|
||||
} else {
|
||||
/* Set 16-bit scale for the filter */
|
||||
CAN_FS1R(canport) &= ~filter_select_bit;
|
||||
}
|
||||
|
||||
if (id_list_mode) {
|
||||
/* Set filter mode to id list mode */
|
||||
CAN_FM1R(canport) |= filter_select_bit;
|
||||
} else {
|
||||
/* Set filter mode to id/mask mode */
|
||||
CAN_FM1R(canport) &= ~filter_select_bit;
|
||||
}
|
||||
|
||||
/* Set the first filter register */
|
||||
CAN_FiR1(canport, nr) = fr1;
|
||||
|
||||
/* Set the second filter register */
|
||||
CAN_FiR2(canport, nr) = fr2;
|
||||
|
||||
if (fifo) {
|
||||
/* Select FIFO1 as filter assignement */
|
||||
CAN_FFA1R(canport) |= filter_select_bit;
|
||||
} else {
|
||||
/* Select FIFO0 as filter assignement */
|
||||
CAN_FFA1R(canport) &= ~filter_select_bit;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
/* Activate the filter */
|
||||
CAN_FA1R(canport) |= filter_select_bit;
|
||||
}
|
||||
|
||||
/* Request initialization "leave" */
|
||||
CAN_FMR(canport) &= ~CAN_FMR_FINIT;
|
||||
|
||||
}
|
||||
|
||||
void can_filter_id_mask_16bit_init(u32 canport, u32 nr,
|
||||
u16 id1, u16 mask1,
|
||||
u16 id2, u16 mask2,
|
||||
u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, false, false,
|
||||
((u32)id1 << 16) | (u32)mask1,
|
||||
((u32)id2 << 16) | (u32)mask2,
|
||||
fifo, enable);
|
||||
}
|
||||
|
||||
|
||||
void can_filter_id_mask_32bit_init(u32 canport, u32 nr,
|
||||
u32 id, u32 mask,
|
||||
u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, true, false,
|
||||
id, mask,
|
||||
fifo, enable);
|
||||
}
|
||||
|
||||
void can_filter_id_list_16bit_init(u32 canport, u32 nr,
|
||||
u16 id1, u16 id2,
|
||||
u16 id3, u16 id4,
|
||||
u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, false, true,
|
||||
((u32)id1 << 16) | (u32)id2,
|
||||
((u32)id3 << 16) | (u32)id4,
|
||||
fifo, enable);
|
||||
}
|
||||
|
||||
void can_filter_id_list_32bit_init(u32 canport, u32 nr,
|
||||
u32 id1, u32 id2,
|
||||
u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, true, true,
|
||||
id1, id2,
|
||||
fifo, enable);
|
||||
}
|
||||
|
||||
void can_enable_irq(u32 canport, u32 irq)
|
||||
{
|
||||
|
||||
CAN_IER(canport) |= irq;
|
||||
}
|
||||
|
||||
void can_disable_irq(u32 canport, u32 irq)
|
||||
{
|
||||
|
||||
CAN_IER(canport) &= ~irq;
|
||||
}
|
||||
|
||||
int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 mailbox = 0;
|
||||
int i;
|
||||
|
||||
if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
|
||||
ret = 0;
|
||||
mailbox = CAN_MBOX0;
|
||||
} else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) {
|
||||
ret = 1;
|
||||
mailbox = CAN_MBOX1;
|
||||
} else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) {
|
||||
ret = 2;
|
||||
mailbox = CAN_MBOX2;
|
||||
} else {
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
if (ret != -1) { /* check if we have an empty mailbox */
|
||||
if (ext) {
|
||||
/* Set extended id */
|
||||
CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_EXID_SHIFT;
|
||||
/* Set extended id indicator bit */
|
||||
CAN_TIxR(canport, mailbox) |= CAN_TIxR_IDE;
|
||||
} else {
|
||||
/* Set standard id */
|
||||
CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_STID_SHIFT;
|
||||
/* Unset extended id indicator bit */
|
||||
CAN_TIxR(canport, mailbox) &= ~CAN_TIxR_IDE;
|
||||
}
|
||||
|
||||
if (rtr) {
|
||||
/* Set remote transmission request bit */
|
||||
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR;
|
||||
} else {
|
||||
/* Unset remote transmission request bit */
|
||||
CAN_TIxR(canport, mailbox) &= ~CAN_TIxR_RTR;
|
||||
}
|
||||
|
||||
/* Set the DLC */
|
||||
CAN_TDTxR(canport, mailbox) &= 0xFFFFFFFF0;
|
||||
CAN_TDTxR(canport, mailbox) |= length & CAN_TDTxR_DLC_MASK;
|
||||
|
||||
/* Set the data */
|
||||
CAN_TDLxR(canport, mailbox) = 0;
|
||||
CAN_TDHxR(canport, mailbox) = 0;
|
||||
for (i = 0; (i < 4) && (i < length); i++) {
|
||||
CAN_TDLxR(canport, mailbox) |= (u32)data[i] << (8 * i);
|
||||
}
|
||||
for (i = 4; (i < 8) && (i < length); i++) {
|
||||
CAN_TDHxR(canport, mailbox) |= (u32)data[i] << (8 * (i-4));
|
||||
}
|
||||
|
||||
/* Request transmission */
|
||||
CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void can_fifo_release(u32 canport, u8 fifo)
|
||||
{
|
||||
if (fifo == 0) {
|
||||
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
|
||||
} else {
|
||||
CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
|
||||
}
|
||||
}
|
||||
|
||||
void can_receive(u32 canport, u8 fifo, bool release,
|
||||
u32 *id, bool *ext, bool *rtr, u32 *fmi,
|
||||
u8 *length, u8 *data)
|
||||
{
|
||||
u32 fifo_id = 0;
|
||||
int i;
|
||||
|
||||
if (fifo == 0) {
|
||||
fifo_id = CAN_FIFO0;
|
||||
} else {
|
||||
fifo_id = CAN_FIFO1;
|
||||
}
|
||||
|
||||
/* get type of CAN id and CAN id */
|
||||
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
|
||||
*ext = true;
|
||||
/* Get extended CAN id */
|
||||
*id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_EXID_MASK) >
|
||||
CAN_RIxR_EXID_SHIFT);
|
||||
} else {
|
||||
*ext = false;
|
||||
/* Get standard CAN id */
|
||||
*id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_STID_MASK) >
|
||||
CAN_RIxR_STID_SHIFT);
|
||||
}
|
||||
|
||||
/* get request transmit flag */
|
||||
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
|
||||
*rtr = true;
|
||||
} else {
|
||||
*rtr = false;
|
||||
}
|
||||
|
||||
/* get filter match id */
|
||||
*fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) >
|
||||
CAN_RDTxR_FMI_SHIFT);
|
||||
|
||||
/* get data length */
|
||||
*length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
|
||||
|
||||
/* get data */
|
||||
for (i=0; (i < 4) && (i < *length); i++) {
|
||||
data[i] = (CAN_RDLxR(canport, fifo_id) >> (8 * i)) & 0xFF;
|
||||
}
|
||||
|
||||
for (i=4; (i < 8) && (i < *length); i++) {
|
||||
data[i] = (CAN_RDHxR(canport, fifo_id) >> (8 * (i - 4))) & 0xFF;
|
||||
}
|
||||
|
||||
/* release the fifo */
|
||||
if (release) {
|
||||
can_fifo_release(CAN1, 0);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue