doc: stm32: rtc common v2: convert comments to doxygen
Grouping and making the existing comments doxygen friendly
This commit is contained in:
Karl Palsson
parent
22f7348b89
commit
e076c3cadd
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@ -40,149 +40,195 @@ specific memorymap.h header before including this header file.*/
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#ifndef LIBOPENCM3_RTC2_H
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#define LIBOPENCM3_RTC2_H
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/**@{*/
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/** @defgroup rtc_registers RTC Registers
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* @ingroup rtc_defines
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* @brief Real Time Clock registers
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@{*/
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/* RTC time register (RTC_TR) */
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/** RTC time register (RTC_TR) */
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#define RTC_TR MMIO32(RTC_BASE + 0x00)
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/* RTC date register (RTC_DR) */
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/** RTC date register (RTC_DR) */
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#define RTC_DR MMIO32(RTC_BASE + 0x04)
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/* RTC control register (RTC_CR) */
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/** RTC control register (RTC_CR) */
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#define RTC_CR MMIO32(RTC_BASE + 0x08)
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/* RTC initialization and status register (RTC_ISR) */
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/** RTC initialization and status register (RTC_ISR) */
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#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
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/* RTC prescaler register (RTC_PRER) */
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/** RTC prescaler register (RTC_PRER) */
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#define RTC_PRER MMIO32(RTC_BASE + 0x10)
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/* RTC wakeup timer register (RTC_WUTR) */
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/** RTC wakeup timer register (RTC_WUTR) */
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#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
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/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
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/** RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
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#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
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/* RTC alarm X register (RTC_ALRMxR) */
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/** RTC alarm X register (RTC_ALRMxR) */
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#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
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#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
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/* RTC write protection register (RTC_WPR)*/
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/** RTC write protection register (RTC_WPR)*/
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#define RTC_WPR MMIO32(RTC_BASE + 0x24)
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/* RTC sub second register (RTC_SSR) (high and med+ only) */
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/** RTC sub second register (RTC_SSR) (high and med+ only) */
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#define RTC_SSR MMIO32(RTC_BASE + 0x28)
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/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
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/** RTC shift control register (RTC_SHIFTR) (high and med+ only) */
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#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
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/* RTC time stamp time register (RTC_TSTR) */
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/** RTC time stamp time register (RTC_TSTR) */
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#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
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/* RTC time stamp date register (RTC_TSDR) */
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/** RTC time stamp date register (RTC_TSDR) */
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#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
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/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
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/** RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
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#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
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/* RTC calibration register (RTC_CALR) (high and med+ only) */
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/** RTC calibration register (RTC_CALR) (high and med+ only) */
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#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
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/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
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/** RTC tamper and alternate function configuration register (RTC_TAFCR) */
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#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
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/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
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/** RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
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#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
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#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
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/* RTC backup registers (RTC_BKPxR) */
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#define RTC_BKP_BASE (RTC_BASE + 0x50)
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/** RTC backup registers (RTC_BKPxR) */
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#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4 * (reg)))
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/*@}*/
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/* RTC time register (RTC_TR) ----------------------------------- */
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/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
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*/
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#define RTC_TR_PM (1 << 22) /* AM/PM notation */
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#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */
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#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */
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#define RTC_TR_HU_SHIFT (16) /* Hour units in BCD format shift */
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#define RTC_TR_HU_MASK (0xf) /* Hour units in BCD format mask */
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#define RTC_TR_MNT_SHIFT (12) /* Minute tens in BCD format shift */
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#define RTC_TR_MNT_MASK (0x7) /* Minute tens in BCD format mask */
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#define RTC_TR_MNU_SHIFT (8) /* Minute units in BCD format shift */
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#define RTC_TR_MNU_MASK (0xf) /* Minute units in BCD format mask */
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#define RTC_TR_ST_SHIFT (4) /* Second tens in BCD format shift */
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#define RTC_TR_ST_MASK (0x7) /* Second tens in BCD format mask */
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#define RTC_TR_SU_SHIFT (0) /* Second units in BCD format shift */
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#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */
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/* RTC date register (RTC_DR) ----------------------------------- */
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/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
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*/
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#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */
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#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */
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#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */
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#define RTC_DR_YU_MASK (0xf) /* Year units in BCD format mask */
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#define RTC_DR_WDU_SHIFT (13) /* Weekday units shift */
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#define RTC_DR_WDU_MASK (0x7) /* Weekday units mask */
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#define RTC_DR_MT (1<<12) /* Month tens in BCD format shift */
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#define RTC_DR_MT_SHIFT (12) /* Month tens in BCD format mask */
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#define RTC_DR_MU_SHIFT (8) /* Month units in BCD format shift */
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#define RTC_DR_MU_MASK (0xf) /* Month units in BCD format mask */
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#define RTC_DR_DT_SHIFT (4) /* Date tens in BCD format shift */
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#define RTC_DR_DT_MASK (0x3) /* Date tens in BCD format mask */
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#define RTC_DR_DU_SHIFT (0) /* Date units in BCD format shift */
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#define RTC_DR_DU_MASK (0xf) /* Date units in BCD format mask */
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/** @defgroup rtc_tr_values RTC Time register (RTC_TR) values
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* @ingroup rtc_registers
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* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
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@{*/
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/** AM/PM notation */
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#define RTC_TR_PM (1 << 22)
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/** Hour tens in BCD format shift */
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#define RTC_TR_HT_SHIFT (20)
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/** Hour tens in BCD format mask */
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#define RTC_TR_HT_MASK (0x3)
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/** Hour units in BCD format shift */
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#define RTC_TR_HU_SHIFT (16)
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/** Hour units in BCD format mask */
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#define RTC_TR_HU_MASK (0xf)
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/** Minute tens in BCD format shift */
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#define RTC_TR_MNT_SHIFT (12)
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/** Minute tens in BCD format mask */
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#define RTC_TR_MNT_MASK (0x7)
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/** Minute units in BCD format shift */
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#define RTC_TR_MNU_SHIFT (8)
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/** Minute units in BCD format mask */
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#define RTC_TR_MNU_MASK (0xf)
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/** Second tens in BCD format shift */
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#define RTC_TR_ST_SHIFT (4)
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/** Second tens in BCD format mask */
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#define RTC_TR_ST_MASK (0x7)
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/** Second units in BCD format shift */
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#define RTC_TR_SU_SHIFT (0)
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/** Second units in BCD format mask */
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#define RTC_TR_SU_MASK (0xf)
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/*@}*/
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/* RTC control register (RTC_CR) -------------------------------- */
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/* Note: Bits [31:24] are reserved, and must be kept at reset value. */
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/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode
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/** @defgroup rtc_dr_values RTC Date register (RTC_DR) values
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* @ingroup rtc_registers
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* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
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@{*/
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/** Year tens in BCD format shift */
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#define RTC_DR_YT_SHIFT (20)
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/** Year tens in BCD format mask */
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#define RTC_DR_YT_MASK (0xf)
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/** Year units in BCD format shift */
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#define RTC_DR_YU_SHIFT (16)
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/** Year units in BCD format mask */
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#define RTC_DR_YU_MASK (0xf)
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/** Weekday units shift */
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#define RTC_DR_WDU_SHIFT (13)
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/** Weekday units mask */
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#define RTC_DR_WDU_MASK (0x7)
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/** Month tens in BCD format shift */
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#define RTC_DR_MT (1<<12)
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/** Month tens in BCD format mask */
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#define RTC_DR_MT_SHIFT (12)
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/** Month units in BCD format shift */
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#define RTC_DR_MU_SHIFT (8)
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/** Month units in BCD format mask */
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#define RTC_DR_MU_MASK (0xf)
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/** Date tens in BCD format shift */
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#define RTC_DR_DT_SHIFT (4)
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/** Date tens in BCD format mask */
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#define RTC_DR_DT_MASK (0x3)
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/** Date units in BCD format shift */
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#define RTC_DR_DU_SHIFT (0)
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/** Date units in BCD format mask */
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#define RTC_DR_DU_MASK (0xf)
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/*@}*/
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/** @defgroup rtc_cr_values RTC control register (RTC_CR) values
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* @ingroup rtc_registers
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* Note: Bits [31:24] are reserved, and must be kept at reset value.
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* Note: Bits 7, 6 and 4 of this register can be written in initialization mode
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* only (RTC_ISR/INITF = 1).
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*/
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@{*/
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/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit
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* = 0 and RTC_ISR WUTWF bit = 1.
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*/
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#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */
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/** Calibration output enable */
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#define RTC_CR_COE (1<<23)
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/* RTC_CR_OSEL: Output selection values */
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/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC
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* output
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*/
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#define RTC_CR_OSEL_SHIFT 21
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#define RTC_CR_OSEL_MASK (0x3)
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/** @defgroup rtc_cr_osel RTC_CR_OSEL: Output selection values
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* @ingroup rtc_cr_values
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* These bits are used to select the flag to be routed to AFO_ALARM RTC output
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@{*/
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#define RTC_CR_OSEL_DISABLED (0x0)
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#define RTC_CR_OSEL_ALARMA (0x1)
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#define RTC_CR_OSEL_ALARMB (0x2)
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#define RTC_CR_OSEL_WAKEUP (0x3)
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/*@}*/
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#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */
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#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output
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selection */
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#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */
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#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour
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(winter time change) */
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#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer
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time change) */
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#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt
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enable */
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#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer
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interrupt enable */
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#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt
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enable */
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#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt
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enable */
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#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */
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#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */
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#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */
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#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */
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#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital
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calibration enable */
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#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */
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#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow
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registers */
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#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock
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detection enable */
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#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event
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active edge */
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/** Output polarity */
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#define RTC_CR_POL (1<<20)
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/** Calibration output selection */
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#define RTC_CR_COSEL (1<<19)
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/** Backup */
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#define RTC_CR_BKP (1<<18)
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/** Subtract 1 hour (winter time change) */
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#define RTC_CR_SUB1H (1<<17)
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/** Add 1 hour (summer time change) */
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#define RTC_CR_ADD1H (1<<16)
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/** Timestamp interrupt enable */
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#define RTC_CR_TSIE (1<<15)
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/** Wakeup timer interrupt enable */
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#define RTC_CR_WUTIE (1<<14)
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/** Alarm B interrupt enable */
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#define RTC_CR_ALRBIE (1<<13)
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/** Alarm A interrupt enable */
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#define RTC_CR_ALRAIE (1<<12)
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/** Time stamp enable */
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#define RTC_CR_TSE (1<<11)
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/** Wakeup timer enable */
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#define RTC_CR_WUTE (1<<10)
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/** Alarm B enable */
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#define RTC_CR_ALRBE (1<<9)
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/** Alarm A enable */
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#define RTC_CR_ALRAE (1<<8)
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/** Course digital calibration enable */
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#define RTC_CR_DCE (1<<7)
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/** Hour format */
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#define RTC_CR_FMT (1<<6)
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/** Bypass the shadow registers */
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#define RTC_CR_BYPSHAD (1<<5)
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/** Reference clock detection enable */
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#define RTC_CR_REFCKON (1<<4)
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/** Timestamp event active edge */
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#define RTC_CR_TSEDGE (1<<3)
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/* RTC_CR_WUCKSEL: Wakeup clock selection */
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#define RTC_CR_WUCLKSEL_SHIFT (0)
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@ -193,34 +239,61 @@ specific memorymap.h header before including this header file.*/
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#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
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#define RTC_CR_WUCLKSEL_SPRE (0x4)
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#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
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/*@}*/
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/* RTC initialization and status register (RTC_ISR) ------------- */
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/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */
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/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */
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#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */
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#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag
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(not on F4)*/
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#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */
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#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */
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#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */
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#define RTC_ISR_TSF (1<<11) /* TSF: Timestamp flag */
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#define RTC_ISR_WUTF (1<<10) /* WUTF: Wakeup timer flag */
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#define RTC_ISR_ALRBF (1<<9) /* ALRBF: Alarm B flag */
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#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */
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#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */
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#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */
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#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */
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#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */
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#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */
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#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */
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#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */
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#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */
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/** @defgroup rtc_isr_values RTC initialization and status register (RTC_ISR) values
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* @ingroup rtc_registers
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* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value.
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* Note: This register is write protected (except for RTC_ISR[13:8] bits).
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@{*/
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/** RECALPF: Recalib pending flag */
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#define RTC_ISR_RECALPF (1<<16)
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/** TAMP3F: TAMPER3 detection flag (not on F4)*/
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#define RTC_ISR_TAMP3F (1<<15)
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/** TAMP2F: TAMPER2 detection flag */
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#define RTC_ISR_TAMP2F (1<<14)
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/** TAMP1F: TAMPER detection flag */
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#define RTC_ISR_TAMP1F (1<<13)
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/** TSOVF: Timestamp overflow flag */
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#define RTC_ISR_TSOVF (1<<12)
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/** TSF: Timestamp flag */
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#define RTC_ISR_TSF (1<<11)
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/** WUTF: Wakeup timer flag */
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#define RTC_ISR_WUTF (1<<10)
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/** ALRBF: Alarm B flag */
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#define RTC_ISR_ALRBF (1<<9)
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/** ALRAF: Alarm A flag */
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#define RTC_ISR_ALRAF (1<<8)
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/** INIT: Initialization mode */
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#define RTC_ISR_INIT (1<<7)
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/** INITF: Initialization flag */
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#define RTC_ISR_INITF (1<<6)
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/** RSF: Registers sync flag */
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#define RTC_ISR_RSF (1<<5)
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/** INITS: Init status flag */
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#define RTC_ISR_INITS (1<<4)
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/** SHPF: Shift operation pending */
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#define RTC_ISR_SHPF (1<<3)
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/** WUTWF: Wakeup timer write flag */
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#define RTC_ISR_WUTWF (1<<2)
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/** ALRBWF: Alarm B write flag */
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#define RTC_ISR_ALRBWF (1<<1)
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/** ALRAWF: Alarm A write flag */
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#define RTC_ISR_ALRAWF (1<<0)
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/*@}*/
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/* RTC prescaler register (RTC_PRER) ---------------------------- */
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#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */
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#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */
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#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */
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#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */
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/** @defgroup rtc_prer_values RTC prescaler register (RTC_PRER) values
|
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* @ingroup rtc_registers
|
||||
@{*/
|
||||
/** Async prescaler factor shift */
|
||||
#define RTC_PRER_PREDIV_A_SHIFT (16)
|
||||
/** Async prescaler factor mask */
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||||
#define RTC_PRER_PREDIV_A_MASK (0x7f)
|
||||
/** Sync prescaler factor shift */
|
||||
#define RTC_PRER_PREDIV_S_SHIFT (0)
|
||||
/** Sync prescaler factor mask */
|
||||
#define RTC_PRER_PREDIV_S_MASK (0x7fff)
|
||||
/*@}*/
|
||||
|
||||
/* RTC calibration register (RTC_CALIBR) ------------------------ */
|
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#define RTC_CALIBR_DCS (1 << 7)
|
||||
|
|
@ -228,8 +301,10 @@ specific memorymap.h header before including this header file.*/
|
|||
#define RTC_CALIBR_DC_SHIFT (0)
|
||||
#define RTC_CALIBR_DC_MASK (0x1f)
|
||||
|
||||
/* RTC Alarm register ------------------------------------------- */
|
||||
/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */
|
||||
/** @defgroup rtc_alarm_values RTC Alarm register values
|
||||
* @ingroup rtc_registers
|
||||
* Applies to RTC_ALRMAR and RTC_ALRMBR
|
||||
@{*/
|
||||
#define RTC_ALRMXR_MSK4 (1<<31)
|
||||
#define RTC_ALRMXR_WDSEL (1<<30)
|
||||
#define RTC_ALRMXR_DT_SHIFT (28)
|
||||
|
|
@ -252,6 +327,7 @@ specific memorymap.h header before including this header file.*/
|
|||
#define RTC_ALRMXR_ST_MASK (0x7)
|
||||
#define RTC_ALRMXR_SU_SHIFT (0)
|
||||
#define RTC_ALRMXR_SU_MASK (0xf)
|
||||
/*@}*/
|
||||
|
||||
/* RTC shift control register (RTC_SHIFTR) ---------------------- */
|
||||
#define RTC_SHIFTR_ADD1S (31)
|
||||
|
|
@ -259,7 +335,9 @@ specific memorymap.h header before including this header file.*/
|
|||
#define RTC_SHIFTR_SUBFS_SHIFT (0)
|
||||
#define RTC_SHIFTR_SUBFS_MASK (0x7fff)
|
||||
|
||||
/* RTC time stamp time register (RTC_TSTR) ---------------------- */
|
||||
/** @defgroup rtc_tstr_values RTC time stamp time register (RTC_TSTR) values
|
||||
* @ingroup rtc_registers
|
||||
@{*/
|
||||
#define RTC_TSTR_PM (1<<22)
|
||||
#define RTC_TSTR_HT_SHIFT (20)
|
||||
#define RTC_TSTR_HT_MASK (0x3)
|
||||
|
|
@ -273,8 +351,11 @@ specific memorymap.h header before including this header file.*/
|
|||
#define RTC_TSTR_ST_MASK (0x7)
|
||||
#define RTC_TSTR_SU_SHIFT (0)
|
||||
#define RTC_TSTR_SU_MASK (0xf)
|
||||
/*@}*/
|
||||
|
||||
/* RTC time stamp date register (RTC_TSDR) ---------------------- */
|
||||
/** @defgroup rtc_tsdr_values RTC time stamp date register (RTC_TSDR) values
|
||||
* @ingroup rtc_registers
|
||||
@{*/
|
||||
#define RTC_TSDR_WDU_SHIFT (13)
|
||||
#define RTC_TSDR_WDU_MASK (0x7)
|
||||
#define RTC_TSDR_MT (1<<12)
|
||||
|
|
@ -284,15 +365,21 @@ specific memorymap.h header before including this header file.*/
|
|||
#define RTC_TSDR_DT_MASK (0x3)
|
||||
#define RTC_TSDR_DU_SHIFT (0)
|
||||
#define RTC_TSDR_DU_MASK (0xf)
|
||||
/*@}*/
|
||||
|
||||
/* RTC calibration register (RTC_CALR) -------------------------- */
|
||||
/** @defgroup rtc_calr_values RTC calibration register (RTC_CALR) values
|
||||
* @ingroup rtc_registers
|
||||
@{*/
|
||||
#define RTC_CALR_CALP (1 << 15)
|
||||
#define RTC_CALR_CALW8 (1 << 14)
|
||||
#define RTC_CALR_CALW16 (1 << 13)
|
||||
#define RTC_CALR_CALM_SHIFT (0)
|
||||
#define RTC_CALR_CALM_MASK (0x1ff)
|
||||
/*@}*/
|
||||
|
||||
/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */
|
||||
/** @defgroup rtc_tafcr_values RTC tamper and alternate function configuration register (RTC_TAFCR) values
|
||||
* @ingroup rtc_registers
|
||||
@{*/
|
||||
#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
|
||||
#define RTC_TAFCR_TAMPPUDIS (1<<15)
|
||||
|
||||
|
|
@ -329,6 +416,7 @@ specific memorymap.h header before including this header file.*/
|
|||
#define RTC_TAFCR_TAMPIE (1<<2)
|
||||
#define RTC_TAFCR_TAMP1TRG (1<<1)
|
||||
#define RTC_TAFCR_TAMP1E (1<<0)
|
||||
/*@}*/
|
||||
|
||||
/* RTC alarm X sub second register ------------------------------ */
|
||||
/* Note: Applies to RTC_ALRMASSR and RTC_ALRMBSSR */
|
||||
|
|
|
|||
Loading…
Reference in New Issue